PIC16LF1847T-I/MV Microchip Technology, PIC16LF1847T-I/MV Datasheet - Page 21

• Manufacturer Part Number: PIC16LF1847T-I/MV
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16LF1847T-I/MV

• Processor Series: PIC16LF
• Core: RISC
• Data Bus Width: 10 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 1024 B
• Interface Type: SPI, I2C
• Maximum Clock Frequency: 32 KHZ
• Number Of Programmable I/os: 15
• Number Of Timers: 3
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-28
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: PIC16F1847T
• Supply Current (max): 34 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details

3.2
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers
Addressing”
3.2.1
The core registers contain the registers that directly
affect the basic operation of the PIC16F/LF1847. These
registers are listed below:
• INDF0
• INDF1
• PCL
• STATUS
• FSR0 Low
• FSR0 High
• FSR1 Low
• FSR1 High
• BSR
• WREG
• PCLATH
• INTCON
 2011 Microchip Technology Inc.
Note:
3-2):
Data Memory Organization
CORE REGISTERS
The core registers are the first 12
addresses of every data memory bank.
(FSR).
for more information.
See
Section 3.5
“Indirect
Preliminary
3.2.1.1
The STATUS register, shown in
• the arithmetic status of the ALU
• the Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to
“Instruction Set
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
STATUS Register
PIC16(L)F1847
Summary”).
Register
DS41453B-page 21
3-1, contains:
Section 29.0