LTC1289BCN Linear Technology, LTC1289BCN Datasheet
LTC1289BCN
Specifications of LTC1289BCN
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LTC1289BCN Summary of contents
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... This allows easy interface to shift registers and a variety of processors. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. LTCMOS is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Single Cell 3V 12-Bit Data Acquisition System V ...
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... JMAX JA OBSOLETE PACKAGE Consider the N Package for Alternate Source ORDER PART NUMBER LTC1289BCN LTC1289CCN Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ...
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VERTER A D ULTIPLEXER CHARACTERISTICS which apply over the full operating temperature range, otherwise specifications are at T PARAMETER CONDITIONS Minimum Resolution for Which No Missing Codes are Guaranteed Analog and REF Input Range (Note 7) ...
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LTC1289 U DIGITAL A D ELECTRICAL C DC apply over the full operating temperature range, otherwise specifications are at T SYMBOL PARAMETER V High Level Input Voltage IH V Low Level Input Voltage IL I High Level Input Current IH ...
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W U TYPICAL PERFOR A Supply Current vs Supply Voltage 2.8 ACLK = 2MHz 2 25°C A 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE ...
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LTC1289 W U TYPICAL PERFOR A Maximum Filter Resistor vs Cycle Time 10k 1k 100 R FILTER + V IN ≥ 1µF C FILTER 10 – 100 1000 10000 CYCLE TIME (µs) LTC1289 TPC10 Supply Current (Power Shutdown) ...
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CTIO S CH0 – CH7 (Pins 1 – 8): Analog Inputs. The analog in- puts must be free of noise with respect to AGND. COM (Pin 9): Common. The common pin defines the zero reference ...
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LTC1289 TEST CIRCUITS On and Off Channel Leakage Current OFF A POLARITY Load Circuit for dDO 1. OUT 100pF ACLK CS D OUT WAVEFORM 1 (SEE NOTE 1) D OUT ...
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PPLICATI S I FOR ATIO A The LTC1289 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive A/D converter 2. Analog multiplexer (MUX) 3. Sample-and-hold (S/H) 4. Synchronous, full duplex ...
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LTC1289 PPLICATI S I FOR ATIO MUX Address The first four bits of the input word assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between ...
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PPLICATI S I FOR ATIO Unipolar/Bipolar (UNI) The fifth input bit (UNI) determines whether the conver- sion will be unipolar or bipolar. When UNI is a logical one, a unipolar conversion will be performed on the ...
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LTC1289 PPLICATI S I FOR ATIO The following discussion will demonstrate how the two reference pins are to be used in conjunction with the analog input multiplexer. In unipolar mode the input span of the A/D ...
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PPLICATI S I FOR ATIO 8-Bit Word Length CS SCLK 1 D OUT B11 B10 MSB-FIRST (SB) D OUT B0 B1 LSB-FIRST 12-Bit Word Length CS 1 SCLK (SB) D OUT B11 B10 MSB-FIRST D OUT ...
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LTC1289 PPLICATI S I FOR ATIO Deglitcher A deglitching circuit has been added to the Chip Select input of the LTC1289 to minimize the effects of errors caused by noise on that input. This circuit ignores ...
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PPLICATI S I FOR ATIO A Logic Levels The logic level standards for this supply range have not been well defined. What standards that do exist are not universally accepted. The trip point on the logic inputs ...
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LTC1289 PPLICATI S I FOR ATIO Figure 6 shows an example of an ideal ground plane design for a two-sided board. Of course, this much ground plane will not always be possible, but users should strive ...
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PPLICATI FOR ATIO 3. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1289 have capacitive switching input current spikes. These current spikes settle quickly and do ...
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LTC1289 PPLICATI S I FOR ATIO A settling can be extended by using a slower ACLK fre- quency. At the maximum ACLK rate of 2MHz, R Ω 200 and C2 < 20pF will provide adequate settling. Input ...
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PPLICATI S I FOR ATIO pins on the package ends (DGND and CH0). Grounding any unused inputs (especially the end pin, CH0) will also reduce outside coupling into high source resistances. 4. Sample and Hold Single-Ended ...
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LTC1289 PPLICATI S I FOR ATIO HORIZONTAL: 1µs/DIV Figure 15. Adequate Reference Settling HORIZONTAL: 1µs/DIV Figure 16. Poor Reference Settling Can Cause A/D Errors – recommended that REF input be tied directly to ...
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PPLICATI S I FOR ATIO 7. LTC1289 AC Characteristics Two commonly used figures of merit for specifying the dynamic performance of the A/D’s in digital signal pro- cessing applications are the Signal-to-Noise Ratio (SNR) and the ...
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LTC1289 PPLICATI FOR ATIO Figure 19 shows an FFT plot of the output spectrum for two tones applied to the input of the A/D. Nonlinearities in the A/D will cause distortion products at the ...
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... CLR2 74HC393 2QA 2QB 2QC 2QD LTC1289 TA02 OTHER CHANNELS OR SNEAK-A-BIT INPUTS V –2.5V TO +2.5V ) HEX V IN 1ST CONVERSION FILLS ZEROES 2ND CONVERSION SNEAK-A-BIT is a trademark of Linear Technology Corp. LTC1289 TM SNEAK-A-BIT Circuit 22µF +3.3V 2MHz ACLK CHO CH1 ACLK CH2 SCLK D CH3 IN D ...
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LTC1289 U O TYPICAL A PPLICATI SNEAK-A-BIT Code D from LTC1289 in MC68HC05C4 RAM OUT Sign Location $77 B12 B11 B10 Location $ filled with 0s D words for LTC1289 ...
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U O TYPICAL A PPLICATI Power Shutdown For battery-powered applications it is desirable to keep power dissipation at a minimum. The LTC1289 can be powered down when not in use reducing the supply current from a nominal value of 1mA ...
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LTC1289 TYPICAL PPLICATI CS 1 SCLK PACKAGE DESCRIPTIO CORNER LEADS OPTION (4 PLCS) 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION 0.300 BSC (0.762 BSC) 0.008 – ...
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... MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights. ...
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... NOTE .394 – .419 (10.007 – 10.643) N .037 – .045 (0.940 – 1.143) .004 – .012 (0.102 – 0.305) S20 (WIDE) 0502 , Low Power, 16-Pin SO and SSOP Package REF LT 0506 REV B • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1992 1289fb ...