HI7188IN Intersil, HI7188IN Datasheet - Page 7

• Manufacturer Part Number: HI7188IN
• Description: CONV A/D 16BIT 8:1 MUX 44-MQFP
• Manufacturer: Intersil

Specifications of HI7188IN

• Number Of Bits: 16
• Sampling Rate (per Second): 240
• Data Interface: QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 50mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Specifications
NOTES:
TIMING CHARACTERISTICS
SCLK Minimum Cycle Time, t
SCLK Minimum Pulse Width, t
CS to SCLK Precharge Time, t
Data Setup to SCLK Rising Edge (Write),
t
Data Hold from SCLK Rising Edge
(Write), t
Data Read Access from Instruction Byte
Write, t
Read Bit Valid from SCLK Falling Edge,
t
Last Data Transfer to Data Ready
Inactive, t
RESET Low Pulse Width t
RSTI/O Low Pulse Width t
MUX High Pulse Width t
CADDR Valid to MUX High
Oscillator Clock Frequency
Output Rise/Fall Time
Input Rise/Fall Time
POWER SUPPLY CHARACTERISTICS
IAV
IAV
IDV
Power Dissipation, Active PD
Power Dissipation, Sleep PD
PSRR ( V
2. Parameter guaranteed by design or characterization, not production tested.
3. DC PSRR is measured on all supplies individually and applies to both Bipolar and Unipolar Input Ranges.
4. These errors can be removed by re-calibrating at the desired operating temperature.
5. Applies after system calibration.
6. Fully differential input signal source is used.
7. See Load Test Circuit, Figure 1, R
8. For Line Noise Rejection, 3.6864MHz is required to develop internal clocks to reject 50/60Hz.
9. SLP is the sleep mode enable bit defined in bit 3 of the Control Register (CR <3>).
DSU
DV
DD
SS
DD
ACC
DHLD
DRDY
supply
PARAMETER
= 0.25V)
MUX
RESET
RSTI/O
S
A
SCLK
SCLKPW
PRE
7
AV
OSC
DD
1
= 10k , C
IN
= +5V, AV
= 3.6864MHz, Bipolar Input Range Selected (Continued)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
(Notes 2, 7)
AV
AV
DV
AV
(Notes 3, 9)
AV
(Notes 3, 9)
PSRR = 20log ( V
DD
SS
DD
DD
DD
= -5V, OSC
= +5V, OSC
= +5V, SCLK = 4MHz
= +5V, AV
= +5V, AV
L
SS
= 50pF (Includes Stray and Jig Capacitance).
= -5V, DV
TEST CONDITION
SS
SS
1
supply
1
= 3.6864MHz (Note 3)
= -5V, SLP = ‘0’
= -5V, SLP = ‘1’
= 3.6864MHz (Note 3)
DD
HI7188
= +5V, V
/ V
OS
) (Note 3)
RHI
= +2.5V, V
RLO
MIN
= AGND, V
200
100
100
60
50
50
14
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-40
CM
o
C TO 85
3.6864
TYP
1.8
1.8
2.0
= AGND, PGIA Gain = 1,
50
28
75
5
-
-
-
-
-
-
-
-
-
-
-
-
-
o
C
MAX
3.0
3.0
4.0
40
40
75
30
50
1
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
MHz
mW
mW
mA
mA
mA
dB
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s