LTC2351HUH-14#PBF Linear Technology, LTC2351HUH-14#PBF Datasheet - Page 5

• Manufacturer Part Number: LTC2351HUH-14#PBF
• Description: IC ADC 14BIT 1.5MSPS 32-QFN
• Manufacturer: Linear Technology

Specifications of LTC2351HUH-14#PBF

• Number Of Bits: 14
• Sampling Rate (per Second): 1.5M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 16.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
Note 5: Integral linearity is tested with an external 2.55V reference and is
defi ned as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band. Linearity is tested for CH0 only.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defi ned for the voltage difference
between CHx
Note 9: The absolute voltage at CHx
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
TYPICAL PERFORMANCE CHARACTERISTICS
77
74
71
68
65
62
59
56
0.1
SINAD vs Input Frequency
+
and CHx
FREQUENCY (MHz)
–
, x = 0–5.
92
86
80
74
68
62
56
50
0.1
1
SFDR vs Input Frequency
+
and CHx
FREQUENCY (MHz)
235114 G01
–
10
1
must be within this range.
–104
–110
–50
–56
–62
–68
–74
–80
–86
–92
–98
0.1
THD, 2nd and 3rd
vs Input Frequency
235114 G04
UNIPOLAR SINGLE-ENDED
10
FREQUENCY (MHz)
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
96th rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from sleep
mode with one or more cycles at SCK and a 10μF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The conversion process takes 16 clocks for each channel that is
enabled, up to 96 clocks for all six channels.
1
THD
2nd
3rd
77
74
71
56
65
62
59
68
0.1
SNR vs Input Frequency
V
235114 G02
DD
10
= 3V, T
FREQUENCY (MHz)
A
–104
–110
–50
–56
–62
–68
–98
–74
–80
–86
–92
= 25°C
P-P
0.1
THD, 2nd and 3rd
vs Input Frequency
1
BIPOLAR SINGLE-ENDED
input sine wave.
LTC2351-14
FREQUENCY (MHz)
235114 G05
1
10
THD
2nd
3rd
235114fb
235114 G03
5
10