LTC2290IUP#PBF Linear Technology, LTC2290IUP#PBF Datasheet - Page 13

• Manufacturer Part Number: LTC2290IUP#PBF
• Description: IC ADC DUAL 12BIT 10MSPS 64QFN
• Manufacturer: Linear Technology

Specifications of LTC2290IUP#PBF

• Number Of Bits: 12
• Sampling Rate (per Second): 10M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 138mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, A
should be driven with the input signal and A
connected to V
0.5V and 1.5V.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The V
be used to provide the common mode bias level. V
be tied directly to the center tap of a transformer to set the
DC input level or as a reference level to an op amp
differential driver circuit. The V
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2290 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and reactance can
influence SFDR. At the falling edge of CLK, the sample-
and-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when CLK rises, holding the sampled input on
CM
or a quiet reference voltage between
U
U
CM
pin must be bypassed to
W
CM
output pin may
IN
–
U
should be
CM
can
IN
+
the sampling capacitor. Ideally the input circuitry should
be fast enough to fully charge the sampling capacitor
during the sampling period 1/(2F
not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2290 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with V
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100Ω for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
ANALOG
INPUT
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
0.1µF
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
1:1
T1
25Ω
25Ω
0.1µF
25Ω
25Ω
ENCODE
CM
, setting the ADC input
2.2µF
12pF
V
A
A
); however, this is
CM
IN
IN
LTC2290
+
–
LTC2290
13
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