LTC1415CSW#TR Linear Technology, LTC1415CSW#TR Datasheet - Page 8

• Manufacturer Part Number: LTC1415CSW#TR
• Description: IC ADC 12BIT 1.25MSPS SMP 28SOIC
• Manufacturer: Linear Technology

Specifications of LTC1415CSW#TR

• Number Of Bits: 12
• Sampling Rate (per Second): 1.25M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 100mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
LTC1415
CONVERSION DETAILS
The LTC1415 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs (please refer to Digital Interface section for
the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
Referring to Figure 1, the +A
nected to the sample-and-hold capacitors (C
ing the acquire phase and the comparator offset is nulled by
the zeroing switches. In this acquire phase, a minimum
delay of 150ns will provide enough time for the sample-
and-hold capacitors to acquire the analog signal. During
the convert phase the comparator zeroing switches open,
putting the comparator into compare mode. The input
switches the connect C
ferring the differential analog input charge onto the sum-
ming junction. This input charge is successively compared
8
+A
–A
IN
IN
SAMPLE
SAMPLE
+V
Figure 1. Simplified Block Diagram
DAC
–V
DAC
HOLD
HOLD
U
–C
+C
+C
–C
SAMPLE
SAMPLE
SAMPLE
DAC
DAC
INFORMATION
U
SAR
IN
capacitors to ground, trans-
and –A
ZEROING SWITCHES
12
W
+
–
HOLD
HOLD
COMP
IN
LATCHES
OUTPUT
inputs are con-
SAMPLE
LTC1415 • F01
U
) dur-
•
•
•
D11
D0
with the binary weighted charges supplied by the differen-
tial capacitive DAC. Bit decisions are made by the high
speed comparator. At the end of a conversion, the differ-
ential DAC output balances the + A
charges. The SAR contents (a 12-bit data word) which
represents the difference of + A
the 12-bit output latches.
DYNAMIC PERFORMANCE
The LTC1415 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using a FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1415 FFT plot.
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] or
SINAD is the ratio between the RMS amplitude of the
fundamental input frequency to the RMS amplitude of all
other frequency components at the A/D output. The output
is band limited to frequencies from above DC and below
half the sampling frequency. Figure 2 shows a typical
spectral content with a 1.25MHz sampling rate and a
100kHz input. The dynamic performance is excellent for
input frequencies up to the Nyquist limit of 625kHz.
Figure 2. LTC1415 Nonaveraged, 4096 Point FFT
–100
–120
–20
–40
–60
–80
0
0
100
200
FREQUENCY (kHz)
300
f
f
SFDR - 87.5
SINAD = 72.1
SAMPLE
IN
IN
= 99.792kHz
400
and – A
= 1.25MHz
IN
500
LTC1415 • F02
and – A
IN
are loaded into
600
IN
input