LTC1415CSW#TR Linear Technology, LTC1415CSW#TR Datasheet - Page 10

• Manufacturer Part Number: LTC1415CSW#TR
• Description: IC ADC 12BIT 1.25MSPS SMP 28SOIC
• Manufacturer: Linear Technology

Specifications of LTC1415CSW#TR

• Number Of Bits: 12
• Sampling Rate (per Second): 1.25M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 100mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
LTC1415
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa + – nfb, where m and n = 0, 1, 2,
3, etc. For example, the 2nd order IMD terms include
(fa + fb). If the two input sine waves are equal in magni-
tude, the value (in decibels) of the 2nd order IMD products
can be expressed by the following formula:
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1415 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with fre-
quencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
Driving the Analog Input
The differential analog inputs of the LTC1415 are easy to
drive. The inputs may be driven differentially or as a single-
ended input (i.e., the –A
–A
signal that is common mode to both inputs will be reduced
by the common mode rejection of the sample-and-hold
circuit. The inputs draw only one small current spike while
charging the sample-and-hold capacitors at the end of
conversion. During conversion the analog inputs draw
10
IMD fa fb
IN
inputs are sampled at the same instant. Any unwanted
20
Log
U
IN
Amplitude at (fa + fb)
INFORMATION
input is grounded). The +A
U
Amplitude at fa
W
U
IN
and
only a small leakage current. If the source impedance of the
driving circuit is low, then the LTC1415 inputs can be
driven directly. As source impedance increases so will
acquisition time (see Figure 6). For minimum acquisition
time with high source impedance, a buffer amplifier should
be used. The only requirement is that the amplifier driving
the analog input(s) must settle after the small current spike
before the next conversion starts (settling time must be
150ns for full throughput rate).
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (< 100 ) at the closed-loop band-
width frequency. For example, if an amplifier is used in a
gain of +1 and has a unity-gain bandwidth of 50MHz, then
the output impedance at 50MHz should be less than
100 . The second requirement is that the closed-loop
bandwidth must be greater than 20MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
The best choice for an op amp to drive the LTC1415 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifi-
cations are most critical and time domain applications
where DC accuracy and settling time are most critical.
Figure 6. Acquisition Time vs Source Resistance
0.01
0.1
10
1
0.01
SOURCE RESISTANCE (k )
0.1
1
10
1415 F06
100