ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 29

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

1.0 Functional Description
1.4.1 Note Regarding Extended Mode Offset Correction
When using the I or Q channel Offset Adjust registers, the
following information should be noted.
For offset values of +0000 0000 and -0000 0000, the actual
offset is not the same. By changing only the sign bit in this
case, an offset step in the digital output code of about 1/10th
of an LSB is experienced. This is shown more clearly in the
Figure below.
1.5 MULTIPLE ADC SYNCHRONIZATION
The ADC08D500 has the capability to precisely reset its
sampling clock input to DCLK output relationship as deter-
mined by the user-supplied DCLK_RST pulse. This allows
multiple ADCs in a system to have their DCLK (and data)
outputs transition at the same time with respect to the shared
CLK input that they all use for sampling.
The DCLK_RST signal must observe some timing require-
ments that are shown in Figure 6, Figure 7, and Figure 8 of
the Timing Diagrams. The DCLK_RST pulse must be of a
minimum width and its deassertion edge must observe setup
and hold times with respect to the CLK input rising edge.
These times are specified in the AC Electrical Characteris-
tics Table.
Bits 15:7
(LSB)
Addr: Fh (1111b)
(MSB)
D15
Bit 6:0
D7
FIGURE 10. Extended Mode Offset Behavior
D14
D6
1
Fine Adjust Magnitude. Each code value in
this field delays either the "I" channel or the
"Q" channel sample clock (as determined by
the ADS bit of the DES Coarse Adjust
Register) by approximately 0.1 ps. A value of
0000 0000 0b in this field causes zero
adjustment.
adjustment achieved with each code will vary
with the device conditions as well as with the
Coarse Adjustment value chosen.
POR State: 0000 0000 0b
Must be set to 1b
D13
D5
1
DES Fine Adjust
D12
D4
1
Note
D11
D3
1
FAM
that
D10
D2
W only (0x007F)
1
the
D9
D1
amount
20121430
1
(Continued)
D8
D0
1
of
29
The DCLK_RST signal can be asserted asynchronous to the
input clock If DCLK_RST is asserted, the DCLK output is
held in a designated state. The state in which DCLK is held
during the reset period is determined by the mode of opera-
tion (SDR/DDR) and the setting of the Output Edge configu-
ration pin or bit. (Refer to Figure 6, Figure 8, and Figure 8 for
the DCLK reset condictions). Therefore depending upon
when the DCLK_RST signal is asserted, there may be a
narrow pulse on the DCLK line during this reset event. When
the DCLK_RST signal is de-asserted in synchronization with
the CLK rising edge, the next CLK falling edge synchronizes
the DCLK output with those of other ADC08D500s in the
system. The DCLK output is enabled again after a constant
delay which is equal to the CLK input to DCLK output delay
(t
normal operation.
The DCLK-RST pin should NOT be brought high while the
calibration process is running (while CalRun is high). Doing
so could cause a digital glitch in the digital circuitry, resulting
in corruption and invalidation of the calibration.
2.0 Applications Information
2.1 THE REFERENCE VOLTAGE
The voltage reference for the ADC08D500 is derived from a
1.254V bandgap reference which is made available at pin
31, V
capability of
than this is required.
The internal bandgap-derived reference voltage has a nomi-
nal value of 650 mV or 870 mV, as determined by the FSR
pin and described in Section 1.1.4.
There is no provision for the use of an external reference
voltage, but the full-scale input voltage can be adjusted
through a Configuration Register in the Extended Control
mode, as explained in Section 1.2.
Differential input signals up to the chosen full-scale level will
be digitized to 8 bits. Signal excursions beyond the full-scale
range will be clipped at the output. These large signal excur-
sions will also activate the OR output for the time that the
signal is out of range. See Section 2.2.2.
One extra feature of the V
raise the common mode voltage level of the LVDS outputs.
The output offset voltage (V
V
the LVDS offset voltage to a typical value of 1200mV the V
pin can be connected directly to the supply rails.
2.2 THE ANALOG INPUT
The analog input is a differential one to which the signal
source may be a.c. coupled or d.c. coupled. The full-scale
input range is selected with the FSR pin to be 650 mV
870 mV
and 840 mV
Serial Interface. For best performance, it is recommended
that the full-scale range be kept between 595 mV
mV
Table 5 gives the input to output relationship with the FSR
pin high and the normal (non-extended) mode is used. With
the FSR pin grounded, the millivolt values in Table 5 are
reduced to 75% of the values indicated. In the Enhanced
Control Mode, these values will be determined by the full
scale range and offset settings in the Control Registers.
AD
BG
P-P
). The device always exhibits this delay characteristic in
pin is used as an output or left unconnected. To raise
BG
in the Extended Control mode.
P-P
for user convenience and has an output current
, or can be adjusted to values between 560 mV
±
P-P
100 µA and should be buffered if more current
in the Extended Control mode through the
BG
OS
) is typically 800mV when the
pin is that it can be used to
P-P
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and 805
P-P
P-P
BG
or