ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 24

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

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1.0 Functional Description
1.1.4 The Analog Inputs
The ADC08D500 must be driven with a differential input
signal. Operation with a single-ended signal is not recom-
mended. It is important that the inputs either be a.c. coupled
to the inputs with the V
the V
voltage equal to the V
Two full-scale range settings are provided with pin 14 (FSR).
A high on pin 14 causes an input full-scale range setting of
870 mV
range setting of 650 mV
operates equally on both ADCs.
In the Extended Control mode, the full-scale input range can
be set to values between 560 mV
a serial interface. See Section 2.2
1.1.5 Clocking
The ADC08D500 must be driven with an a.c. coupled, differ-
ential clock signal. Section 2.3 describes the use of the clock
input pins. A differential LVDS output clock is available for
use in latching the ADC output data into whatever receives
that data.
The ADC08D500 offers options for input and output clocking.
These options include a choice of Dual Edge Sampling
(DES) or interleaved mode where the ADC08D500 performs
as a single device converting at twice the input clock rate
and a choice of which DCLK edge the output data transitions
on and choice of Single Data Rate (SDR) or Double Data
Rate (DDR) outputs.
The ADC08D500 also has the option to use a duty cycle
corrected clock receiver as part of the input clock circuit. This
feature is enabled by default and provides improved ADC
clocking, especially in the Dual-Edge Sampling mode (DES).
This circuitry allows the ADC to be clocked with a signal
source having a duty cycle ratio of 80 / 20 % (worst case) for
both the normal and the Dual Edge Sampling modes.
1.1.5.2 OutEdge Setting
To help ease data capture in the SDR mode, the output data
may be caused to transition on either the positive or the
negative edge of the output data clock (DCLK). This is
chosen with the OutEdge input (pin 4). A high on the Out-
Edge input causes the output data to transition on the rising
* Note that, in the Dual-Edge Sampling (DES) mode, the "Q" channel input can only be selected for sampling in the
Extended Control Mode.
sourced with respect to
CMO
Data Outputs (Always
P-P
, while grounding pin 14 causes an input full-scale
pin not grounded and an input common mode
fall of DCLK)
DQd
DId
DQ
DI
CMO
CMO
P-P
pin grounded or d.c. coupled with
output.
. The full-scale range setting
TABLE 1. Input Channel Samples Produced at Data Outputs
P-P
"I" Input Sampled with Fall
of CLK 13 cycles earlier.
"I" Input Sampled with Fall
of CLK 14 cycles earlier.
"Q" Input Sampled with Fall
of CLK 13 cycles earlier.
"Q" Input Sampled with Fall
of CLK 14 cycles after being
sampled.
Normal Sampling Mode
and 840 mV
(Continued)
P-P
through
24
"I" Input Sampled with Fall
of CLK 13 cycles earlier.
"I" Input Sampled with Fall
of CLK 14 cycles earlier.
"I" Input Sampled with Rise
of CLK 13.5 cycles earlier.
"I" Input Sampled with Rise
of CLK 14.5 cycles earlier.
1.1.5.1 Dual-Edge Sampling
The DES mode allows one of the ADC08D500’s inputs (I or
Q Channel) to be sampled by both ADCs. One ADC samples
the input on the positive edge of the input clock and the other
ADC samples the same input on the other edge of the input
clock. A single input is thus sampled twice per clock cycle,
resulting in an overall sample rate of twice the input clock
frequency, or 1 GSPS with a 500 MHz clock.
In this mode the outputs are interleaved such that the data is
effectively demultiplexed 1:4. Since the sample rate is
doubled, each of the 4 output buses have a 250 MSPS
output rate with a 500 MHz input clock. All data is available
in parallel. The four bytes of parallel data that is output with
each clock is in the following sampling order, from the earli-
est to the latest: DQd, DId, DQ, DI. Table 1 indicates what
the outputs represent for the various sampling possibilities.
In the non-extended mode of operation only the "I" input can
be sampled in the DES mode. In the extended mode of
operation the user can select which input is sampled.
The ADC08D500 also includes an automatic clock phase
background calibration feature which can be used in DES
mode to automatically and continuously adjust the clock
phase of the I and Q channel. This feature removes the need
to adjust the clock phase setting manually and provides
optimal Dual-Edge Sampling ENOB performance.
IMPORTANT NOTE: The background calibration feature in
DES mode does not replace the requirement for On-
Command Calibration which should be run before entering
DES mode, or if a large swing in ambient temperature is
experienced by the device.
edge of DCLK, while grounding this input causes the output
to transition on the falling edge of DCLK. See Section 2.4.3.
1.1.5.3 Double Data Rate
A choice of single data rate (SDR) or double data rate (DDR)
output is offered. With single data rate the clock frequency is
the same as the data rate of the two output buses. With
I-Channel Selected
Dual-Edge Sampling Mode
"Q" Input Sampled with Fall
of CLK 13 cycles earlier.
"Q" Input Sampled with Fall
of CLK 14 cycles earlier.
"Q" Input Sampled with Rise
of CLK 13.5 cycles earlier.
"Q" Input Sampled with Rise
of CLK 14.5 cycles earlier.
Q-Channel Selected *