ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 12

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

www.national.com
AC ELECTRICAL CHARACTERISTICS
t
CalDly
Symbol
Converter Electrical Characteristics
The following specifications apply after calibration for V
870mV
Floating, Non-Extended Control Mode, SDR Mode, R
tial. Boldface limits apply for T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than V
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
This limit is not placed upon the power, ground and digital output pins.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 5: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
Note 7: To guarantee accuracy, it is required that V
achieving rated performance requires that the backside exposed pad be well grounded.
Note 8: Typical figures are at T
Level).
Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Transfer Characteristic Figure 2. For relationship between Gain Error and Full-Scale
Error, see Specification Definitions for Gain Error.
Note 10: The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to ground
are isolated from the die capacitances by lead and bond wire inductances.
Note 11: This parameter is guaranteed by design and is not tested in production.
Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Note 14: Each of the two converters of the ADC08D500 has two LVDS output buses, which each clock data out at one half the sample rate. The data at each bus
is clocked out at one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one clock cycle less than the latency of the first bus (Dd0
through Dd7)
Note 15: Tying V
supply rail will also affect the differential LVDS output voltage (V
P-P
, C
Calibration delay determined by pin
127
L
BG
= 10 pF, Differential, a.c. coupled Sinewave Input Clock, f
to the supply rail will increase the output offset voltage (V
Parameter
A
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
A
= T
MIN
A
and V
to T
DR
MAX
See Section 1.1.1, Figure 9, (Note
15)
be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
. All other limits T
OD
), causing it to increase by 40mV (typical).
EXT
A
= V
= 3300Ω
DR
Conditions
OS
(Continued)
12
) by 400mv (typical), as shown in the V
= +1.9V
±
A
0.1%, Analog Signal Source Impedance = 100Ω Differen-
= 25˚C, unless otherwise noted. (Notes 6, 7)
DC
20121404
CLK
, OutV = 1.9V, V
= 500 MHz at 0.5V
(Note 8)
Typical
IN
A
), the current at that pin should be limited to
FSR (a.c. coupled) = differential
OS
P-P
specification above. Tying V
with 50% duty cycle, V
(Note 8)
Limits
2
31
Clock Cycles
(Limits)
Units
(max)
BG
to the
BG
=