ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 28

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

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1.0 Functional Description
Bit 15:7
Bits 6:0
(MSB)
Addr: Bh (1011b)
(LSB)
Addr: Dh (1101b)
DEN ACP
D15
D15
Bit 15
D7
D7
1
Q-Channel Full-Scale Voltage Adjust
D14
D14
D6
D6
1
1
Full Scale Voltage Adjust Value. The input
full-scale voltage of the Q-Channel ADC is
adjusted linearly and monotonically from the
nominal 700 mV
in this field.
0000 0000 0
1000 0000 0
1111 1111 1
For best performance, it is recommended
that the value in this field be limited to the
range of 0110 0000 0b to 1110 0000 0b.
i.e., limit the amount of adjustment to
The remaining
the ADC’s own full scale variation .A gain
adjustment does not require ADC
re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
DES Enable. Setting this bit to 1b enables
the Dual Edge Sampling mode. In this mode
the ADCs in this device are used to sample
and convert the same analog input in a
time-interleaved manner, accomplishing a
sampling rate of twice the input clock rate.
When this bit is set to 0b, the device
operates in the normal dual channel mode.
POR State: 0b
D13
D13
D5
D5
1
1
1
DES Enable
D12
D12
D4
D4
1
1
1
Adjust Value
±
P-P
5% headroom allows for
D11
D11
560mV
700mV
840mV
D3
D3
1
1
1
differential by the value
D10
D10
P-P
P-P
P-P
D2
D2
W only (0x3FFF)
W only (0x807F)
1
1
1
D9
D1
D9
D1
1
1
1
(Continued)
±
D8
D0
D8
D0
15%.
1
1
1
28
Bit 14
Bits 13:0
Bit 15
Bits 13:11 Coarse Adjust Magnitude. Each code value
Bits 10:0 Must be set to 1b
Addr: Eh (1110b)
D15
Bit 14
D7
IS
1
ADS
D14
D6
1
Automatic Clock Phase (ACP) Control.
Setting this bit to 1b enables the Automatic
Clock Phase Control. In this mode the DES
Coarse and Fine manual controls are
disabled. A phase detection circuit
continually adjusts the I and Q sampling
edges to be 180 degrees out of phase.
When this bit is set to 0b, the sample (input)
clock delay between the I and Q channels is
set manually using the DES Coarse and
Fine Adjust registers. (See section 2.4.5 for
important application information)Using the
ACP Control option is recommended
over the manual DES settings.
POR State: 0b
Must be set to 1b
Input Select. When this bit is set to 0b the "I"
input is operated upon by both ADCs. When
this bit is set to 1b the "Q" input is operated
on by both ADCs.
POR State: 0b
Adjust Direction Select. When this bit is set
to 0b, the programmed delays are applied to
the "I" channel sample clock while the "Q"
channel sample clock remains fixed. When
this bit is set to 1b, the programmed delays
are applied to the "Q" channel sample clock
while the "I" channel sample clock remains
fixed.
POR State: 0b
in this field delays either the "I" channel or
the "Q" channel sample clock (as
determined by the ADS bit) by
approximately 20 picoseconds. A value of
000b in this field causes zero adjustment.
POR State: 000b
D13
D5
1
DES Coarse Adjust
CAM
D12
D4
1
D11
D3
1
D10
D2
W only (0x07FF)
1
1
D9
D1
1
1
D8
D0
1
1