CS5560-ISZ Cirrus Logic Inc, CS5560-ISZ Datasheet - Page 6

• Manufacturer Part Number: CS5560-ISZ
• Description: IC ADC 24BIT 1CH 50KSPS 24SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5560-ISZ

• Number Of Converters: 1
• Package / Case: 24-SSOP
• Number Of Bits: 24
• Data Interface: Serial
• Power Dissipation (max): 85mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 5 KSPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire, 4-Wire)
• Voltage Reference: 2.5 V
• Supply Voltage (max): 5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 2.5 V to 5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1277 - KIT BOARD FOR CDB5560 ADC598-1273 - DEV BOARD FOR CS5560 W/MUX
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1265-5

SWITCHING CHARACTERISTICS
T
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
6
Master Clock Frequency
Master Clock Duty Cycle
Reset
RST Low Time
RST rising to RDY falling
Conversion
CONV Pulse Width
BP/UP setup to CONV falling
CONV low to start of conversion
Perform Single Conversion (CONV high before RDY falling)
Conversion Time
Sleep Mode
A
= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
7. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.
8. If CONV is held low continuously, conversions occur every 320 MCLK cycles.
9. RDY will fall when the device is fully operational when coming out of sleep mode.
If RDY is tied to CONV, conversions will occur every 322 MCLKs.
If CONV is operated asynchronously to MCLK, a conversion may take up to 324 MCLKs.
RDY falls at the end of conversion.
SLEEP low to low-power state
SLEEP high to device active (Note 9)
Parameter
Start of Conversion to RDY falling
Internal Oscillator
Internal Oscillator
External Clock
External Clock
(Note 7)
(Note 8)
5/4/09
Symbol
t
t
XIN
t
t
t
t
t
t
t
f
wup
cpw
bus
buh
con
con
scn
scn
res
clk
Min
0.5
12
40
20
1
4
0
-
-
-
-
-
-
1536
3083
Typ
120
14
16
50
-
-
-
-
-
-
-
Max
16.2
324
16
60
2
-
-
-
-
-
-
-
-
CS5560
DS713PP2
MCLKs
MCLKs
MCLKs
MCLKs
MCLKs
MCLKs
MHz
MHz
Unit
µs
µs
ns
µs
%