CS5560-ISZ Cirrus Logic Inc, CS5560-ISZ Datasheet - Page 30

• Manufacturer Part Number: CS5560-ISZ
• Description: IC ADC 24BIT 1CH 50KSPS 24SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5560-ISZ

• Number Of Converters: 1
• Package / Case: 24-SSOP
• Number Of Bits: 24
• Data Interface: Serial
• Power Dissipation (max): 85mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 5 KSPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire, 4-Wire)
• Voltage Reference: 2.5 V
• Supply Voltage (max): 5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 2.5 V to 5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1277 - KIT BOARD FOR CDB5560 ADC598-1273 - DEV BOARD FOR CS5560 W/MUX
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1265-5

5/4/09
CS5560
SCLK – Serial Clock Input/Output, Pin 23
The SMODE pin determines whether the SCLK signal is an input or an output signal. SCLK
determines the rate at which data is clocked out of the SDO pin. If the converter is in SSC
mode, the SCLK frequency will be determined by the master clock frequency of the converter
(either MCLK or the internal oscillator). In SEC mode, the user determines the SCLK frequency.
If SMODE = VL (SSC Mode), SCLK will be in a high-impedance state when CS is high.
RDY – Ready, Pin 24
At the end of any conversion RDY falls to indicate that a conversion word has been placed into
the serial port. RDY will return high after all data bits are shifted out of the serial port or two mas-
ter clock cycles before new data becomes available if the CS pin is inactive (high); or two mas-
ter clock cycles before new data becomes available if the user holds CS low but has not started
reading the data from the converter when in SEC mode.
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