CS5560-ISZ Cirrus Logic Inc, CS5560-ISZ Datasheet - Page 16

• Manufacturer Part Number: CS5560-ISZ
• Description: IC ADC 24BIT 1CH 50KSPS 24SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5560-ISZ

• Number Of Converters: 1
• Package / Case: 24-SSOP
• Number Of Bits: 24
• Data Interface: Serial
• Power Dissipation (max): 85mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 5 KSPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire, 4-Wire)
• Voltage Reference: 2.5 V
• Supply Voltage (max): 5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 2.5 V to 5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1277 - KIT BOARD FOR CDB5560 ADC598-1273 - DEV BOARD FOR CS5560 W/MUX
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1265-5

3.4 Analog Input
The analog input of the converter is fully differential with a peak-to-peak input of 4.096 volts on each input.
Therefore, the differential, peak-to-peak input is 8.192 volts. This is illustrated in
These diagrams also illustrate a differential buffer amplifier configuration for driving the CS5560.
The capacitors at the outputs of the amplifiers provide a charge reservoir for the dynamic current from the
A/D inputs while the resistors isolate the dynamic current from the amplifier. The amplifiers can be pow-
ered from higher supplies than those used by the A/D but precautions should be taken to ensure that the
op amp output voltage remains within the power supply limits of the A/D, especially under start-up condi-
tions.
3.5 Output Coding Format
The reference voltage directly defines the input voltage range in both the unipolar and bipolar configura-
tions. In the unipolar configuration (BP/UP low), the first code transition occurs 0.5 LSB above zero, and
the final code transition occurs 1.5 LSBs below VREF. In the bipolar configuration (BP/UP high), the first
code transition occurs 0.5 LSB above -VREF and the last transition occurs 1.5 LSBs below +VREF. See
Table 1
16
NOTE: VREF = (VREF+) - (VREF-)
NOTE: VREF = (VREF+) - (VREF-)
for the output coding of the converter.
Table 1. Output Coding, Two’s Complement
Unipolar Input Voltage
Bipolar Input Voltage
Table 2. Output Coding, Offset Binary
<(-VREF+0.5 LSB)
(VREF/2)-0.5 LSB
>(VREF-1.5 LSB)
>(VREF-1.5 LSB)
-VREF+0.5 LSB
VREF-1.5 LSB
VREF-1.5 LSB
<(+0.5 LSB)
+0.5 LSB
-0.5 LSB
5/4/09
Complement
7F FF FF
7F FF FF
7F FF FE
FF FF FF
FF FF FF
FF FF FF
FF FF FE
7F FF FF
00 00 00
80 00 01
80 00 00
80 00 00
80 00 00
00 00 01
00 00 00
00 00 00
Binary
Offset
Two’s
Figure 6
and
CS5560
DS713PP2
Figure
7.