CS5560-ISZ Cirrus Logic Inc, CS5560-ISZ Datasheet - Page 24

• Manufacturer Part Number: CS5560-ISZ
• Description: IC ADC 24BIT 1CH 50KSPS 24SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5560-ISZ

• Number Of Converters: 1
• Package / Case: 24-SSOP
• Number Of Bits: 24
• Data Interface: Serial
• Power Dissipation (max): 85mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 5 KSPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire, 4-Wire)
• Voltage Reference: 2.5 V
• Supply Voltage (max): 5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 2.5 V to 5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1277 - KIT BOARD FOR CDB5560 ADC598-1273 - DEV BOARD FOR CS5560 W/MUX
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1265-5

5/4/09
CS5560
3.10 Serial Port
The serial port on the CS5560 can operate in two different modes: synchronous self clock (SSC) mode &
synchronous external clock (SEC) mode.
3.10.1 SSC Mode
If the SMODE pin is high (SMODE = VL), the serial port operates in the SSC (Synchronous Self Clock)
mode. In the SSC mode the port shifts out conversion data words with SCLK as an output. SCLK is gen-
erated inside the converter from MCLK. Data is output from the SDO (Serial Data Output) pin. If CS is
high, the SDO and SCLK pins will stay in a high-impedance state. If CS is low when RDY falls, the con-
version data word will be output from SDO MSB first. Data is output on the rising edge of SCLK and should
be latched into the external logic on the subsequent rising edge of SCLK. When all bits of the conversion
word are output from the port the RDY signal will return to high.
3.10.2 SEC Mode
If the SMODE pin is low (SMODE = VLR), the serial port operates in the SEC (Synchronous External
Clock mode). In this mode, the user usually monitors RDY. When RDY falls at the end of a conversion,
the conversion data word is placed into the output data register in the serial port. CS is then activated low
to enable data output. Note that CS can be held low continuously if it is not necessary to have the SDO
output operate in the high impedance state. When CS is taken low (after RDY falls) the conversion data
word is then shifted out of the SDO pin by driving the SCLK pin from system logic external to the converter.
If CS is held low continuously, the RDY signal will fall at the end of a conversion and the conversion data
will be placed into the serial port. If the user starts a read, the user will maintain control over the serial port
until the port is empty. However, if SCLK is not toggled, the converter will overwrite the conversion data
at the completion of the next conversion. If CS is held low and no read is performed, RDY will rise just
prior to the end of the next conversion and then fall to signal that new data has been written into the serial
port.
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