CS5560-ISZ Cirrus Logic Inc, CS5560-ISZ Datasheet
CS5560-ISZ
Specifications of CS5560-ISZ
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CS5560-ISZ Summary of contents
Page 1
... AIN in- puts and the VREF+ input. This significantly reduces the drive requirements of signal sources and reduces errors due to source impedances. The CS5560 is a delta-sigma converter capable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital filter architecture ...
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... Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.1 SSC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.2 SEC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11 Power Supplies & Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.12 Using the CS5560 in Multiplexing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.13 Synchronizing Multiple Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4. PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . 32 8 ...
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... Figure 16. Spectral Performance, -130 Figure 17. Spectral Plot of Noise with Shorted Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 18. Noise Histogram (32k Samples Figure 19. CS5560 Digital Filter Response (DC to fs/ Figure 20. CS5560 Digital Filter Response ( kHz Figure 21. CS5560 Digital Filter Response (DC to 4fs Figure 22. Simple Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 23. More Complex Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 1. Output Coding, Two’ ...
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... V1+ = V2+ = +2.5 V, ±5%; V1- = V2 Figure 6. Bipolar mode unless otherwise stated. (Note 1, 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) 997 Hz, -0.5 dB Input 997 Hz, -0.5 dB Input -0.5 dB Input, 997 Hz -60 dB Input, 997 Hz (Note 4.096) ÷ 16,777,216 = 488 nV. CS5560 = 25°C. A Min Typ Max Unit ±%FS - 0.0005 - - ±0.1 - LSB ...
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... Unipolar Bipolar AIN Buffer On (BUFEN = V+) AIN Buffer Off (BUFEN = V-) (Note 5) VREF+ Buffer On (BUFEN = V+) VREF+ Buffer Off (BUFEN = V-) VREF Normal Operation Buffers On Buffers Off (Note 6) V1+ , V2+ Supplies V1-, V2- Supplies CS5560 Min Typ Max 0 to +VREF ±VREF - 600 - - 130 - 116 130 - 4.2 2.4 4 ...
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... RDY will fall when the device is fully operational when coming out of sleep mode. 6 5/4/09 Symbol Min Internal Oscillator XIN External Clock f clk t res Internal Oscillator t wup External Clock t cpw (Note 7) t scn t scn t bus (Note 8) t buh t con t con CS5560 Typ Max Unit MHz 0.5 16 16.2 MHz µs - 120 - µs - 1536 - MCLKs MCLKs ...
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... SDO and SCLK will be high impedance when CS is high. In some systems SCLK and SDO may require pull-down resistors. 11. SCLK = MCLK/2. MCLK RDY SCLK(o) SDO MSB Figure 1. SSC Mode - Read Timing, CS remaining low (Not to Scale) DS713PP2 5/4/09 (CONTINUED) Symbol Min Pulse Width (low Pulse Width (high MSB–1 CS5560 Typ Max Unit -2 - MCLKs MCLKs t 5 LSB+1 LSB 7 ...
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... SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resistor. 13. SCLK = MCLK/2. MCLK RDY SCLK( SDO MSB Figure 2. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale) 8 5/4/09 (CONTINUED) Symbol Min Pulse Width (low Pulse Width (high MSB–1 CS5560 Typ Max Unit MCLKs MCLKs - - LSB+1 LSB DS713PP2 ...
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... RDY rising after SCLK falling 14. SDO will be high impedance when CS is high. In some systems it may require a pull-down resistor. MCLK RDY SCLK( SDO MSB Figure 3. SEC Mode - Continuous SCLK Read Timing (Not to Scale) DS713PP2 5/4/09 (CONTINUED) Symbol - - (Note 14 CS5560 Min Typ Max Unit SCLK - ...
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... Input Leakage Current Digital Input Pin Capacitance Digital Output Pin Capacitance DIGITAL FILTER CHARACTERISTICS TMIN to TMAX 3.3V, ± 2.5V, ±5% or 1.8V, ±5%; VLR = 0V Parameter Group Delay 10 5/4/ MSB Symbol out Symbol - CS5560 LSB Min Typ Max Unit - - 2 µ Min Typ Max Unit ...
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... Minimum High-level Output Voltage: Maximum Low-level Output Voltage: DS713PP2 5/4/09 Guaranteed Limits Sym VL Min Typ 3.3 1.9 V 2.5 1.6 IH 1.8 1.2 3.3 V 2.5 IL 1.8 3.3 2.9 V 2.5 2.1 OH 1.8 1.65 3.3 V 2.5 OL 1.8 CS5560 Max Unit Conditions V 1.1 0. 0.36 0. 0.44 11 ...
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... V2+ V2- V1- V1+ V2- V2- (Note 16) VREF [VREF+] – [VREF-] Symbol [V1+] – [V1-] (Note 17 |V1-| ] (Note 18) - (Note 19 (AIN and VREF pins) V INA V IND T stg WARNING: CS5560 Min Typ Max 4.75 5.0 5.25 4.75 5.0 5. +2.375 +2.5 +2.625 +2.375 +2.5 +2.625 -2.375 -2.5 -2.625 -2.375 -2 ...
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... SLEEP is asserted (low). 3.1 Converter Operation The CS5560 converts at 50 kSps when synchronously operated (CONV = VLR) from a 16.0 MHz master clock. Conversion is initiated by taking CONV low. A conversion lasts 320 master clock cycles, but if CONV is asynchronous to MCLK there may be an uncertainty of 0-4 MCLK cycles after CONV falls to when a conversion actually begins ...
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... If the converter is operated at maximum throughput, the SSC serial port mode is less likely to cause in- terference to measurements as the SCLK output is synchronized to the MCLK. Alternately, any interfer- ence due to serial port clocking can also be minimized if data is read in the SEC serial port mode when a conversion is not in progress. 14 5/4/09 CS5560 DS713PP2 ...
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... IC to the analog input. Adding a 50 ohm resistor on the external MCLK source significantly reduces this effect. 3.3 Voltage Reference The voltage reference for the CS5560 can range from 2.4 volts to 4.2 volts. A 4.096 volt reference is re- quired to achieve the specified performance. reference with either a single +5 V analog supply or with ±2.5 V. ...
Page 16
... The analog input of the converter is fully differential with a peak-to-peak input of 4.096 volts on each input. Therefore, the differential, peak-to-peak input is 8.192 volts. This is illustrated in These diagrams also illustrate a differential buffer amplifier configuration for driving the CS5560. The capacitors at the outputs of the amplifiers provide a charge reservoir for the dynamic current from the A/D inputs while the resistors isolate the dynamic current from the amplifier ...
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... Typical Connection Diagrams The following figure depicts the CS5560 powered from bipolar analog supplies, +2.5 V and - 2 49 47pF +2.048 V 4.99k -2.048 V 4.99k +2.048 -2.048 V 49 47pF 4.99k 4.99k +2.5 V +4.096 Voltage Reference (NOTE 1) -2.5 V Figure 6. CS5560 Configured Using ± 2.5V Analog Supplies ...
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... The following figure depicts the CS5560 device powered from a single 5V analog supply. 49.9 2.048 V 47pF 4.548 V 2.5 V 4.99k +0.452 V +4.548 V 2.5 V +0.452 V 49.9 4.096 V 47pF 4.99k +5 V +4.096 Voltage Reference (NOTE 1) Figure 7. CS5560 Configured Using a Single 5V Analog Supply 18 5/4/09 4700pF C0G ...
Page 19
... AIN & VREF Sampling Structures The CS5560 uses on-chip buffers on the AIN+, AIN-, and the VREF+ inputs. Buffers provide much higher input impedance and therefore reduce the amount of drive current required from an external source. This helps minimize errors. The Buffer Enable (BUFEN) pin determines if the on-chip buffers are used or not. If the BUFEN pin is connected to the V1+ supply, the buffers will be enabled ...
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... Samples @ 50 kSps Frequency (Hz) Figure 13. Spectral Performance, - 5/4/09 Frequency (Hz) Figure 10. Spectral Performance Frequency (Hz) Figure 12. Spectral Performance, -20 dB Frequency (Hz) Figure 14. Spectral Performance, -100 dB CS5560 5.55 kHz 32k Samples @ 50 kSps 5.55 kHz, -20 dB 32k Samples @ 50 kSps 5.55 kHz, -100 dB 32k Samples @ 50 kSps DS713PP2 ...
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... The signal input for is about 8.2 microvolts peak to peak, or about 17 codes peak to peak. with a signal at about 2.6 microvolts peak to peak, or about 5 codes peak to peak. The CS5560 achieves superb performance with this small signal. And the noise floor exhibits no spurious components due to digital interference from the on chip logic ...
Page 22
... Figure 17. Spectral Plot of Noise with Shorted Input 800 700 600 500 400 300 200 100 0 22 5/4/09 10 100 Frequency (Hz) Output (Codes) Figure 18. Noise Histogram (32k Samples) CS5560 Shorted Input 1M Samples @ 50 kSps 64 Averages 1k 10k 25k Std. Dev. = 19.0 Max - Min = 178 DS713PP2 ...
Page 23
... Figure 19. CS5560 Digital Filter Response (DC to fs/2) Figure 20. CS5560 Digital Filter Response ( kHz) Figure 21. CS5560 Digital Filter Response (DC to 4fs) DS713PP2 5/4/ kSps -0.166 dB -0.3725 dB -0.664 dB 5k 10k 15k Frequency (Hz) -0 ...
Page 24
... Serial Port The serial port on the CS5560 can operate in two different modes: synchronous self clock (SSC) mode & synchronous external clock (SEC) mode. 3.10.1 SSC Mode If the SMODE pin is high (SMODE = VL), the serial port operates in the SSC (Synchronous Self Clock) mode ...
Page 25
... Power Supplies & Grounding The CS5560 can be configured to operate with its analog supply operating from 5V, or with its analog sup- plies operating from ±2.5V. The digital interface supports digital logic operating from either 1.8V, 2.5V, or 3.3V. Figure 6 on page 17 illustrates the device configured to operate from ±2.5V analog. ...
Page 26
... The analog input for the signal to be converted must remain active during the entire conversion until RDY falls. The CS5560 can be used in multiplexing applications, but the system timing for changing the multiplexer channel and for starting a new conversion will depend upon the multiplexer system architecture. ...
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... C0G 49.9 47pF 4.99k 49.9 A1+ 47pF 4700pF C0G 4.99k A2+ 4700pF C0G 49.9 A1- 47pF 4.99k A2- 49.9 47pF 4700pF 4.99k C0G Select A2 Select A1 Select B2 Select C2 Convert on CH3 Convert on CH2 CS5560 CS556x AIN+ SW1 AIN- Select A2 Select A1 Select B1 Select C1 Convert on CH4 Convert on CH1 27 ...
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... V1 V1 BUFEN 8 17 VREF VREF BP/ SLEEP 12 13 CS5560 RDY Ready SCLK Serial Clock Input/Output SDO Serial Data Output VL Logic Interface Power VLR Logic Interface Return MCLK Master Clock V2- Negative Voltage 2 V2+ Positive Voltage 2 DCR Digital Core Regulator CONV Convert VLR2 Logic Interface Return ...
Page 29
... SDO is the output pin for the serial output port. Data from this pin will be output at a rate deter- mined by SCLK and in a format determined by the BP/UP pin. Data is output MSB first and advances to the next data bit on the rising edges of SCLK. SDO will high impedance state when CS is high. DS713PP2 5/4/09 CS5560 29 ...
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... CS pin is inactive (high); or two mas- ter clock cycles before new data becomes available if the user holds CS low but has not started reading the data from the converter when in SEC mode. 30 5/4/09 CS5560 DS713PP2 ...
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... JEDEC #: MO-150 Controlling Dimension is Millimeters. CS5560 1 E1 ∝ END VIEW L MILLIMETERS NOM MAX -- 2.13 0.13 0.25 1.73 1.88 -- 0.38 8.20 8.50 7.80 8.20 5 ...
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... ORDERING INFORMATION Model Linearity CS5560-ISZ 0.0005% 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5560-ISZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 8. REVISION HISTORY Revision Date PP1 MAR 2008 PP2 MAY 2009 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. ...