CS5524-ASZ Cirrus Logic Inc, CS5524-ASZ Datasheet - Page 49

• Manufacturer Part Number: CS5524-ASZ
• Description: IC ADC 24BIT 4CH 20SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5524-ASZ

• Number Of Converters: 1
• Package / Case: 24-SSOP
• Number Of Bits: 24
• Data Interface: Serial
• Power Dissipation (max): 14.8mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 4
• Architecture: Delta-Sigma
• Conversion Rate: 617 SPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire)
• Voltage Reference: 2.5 V
• Supply Voltage (max): 5 V
• Supply Voltage (min): 25 mV
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 25 mV to 5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1012 - EVAL BOARD FOR CS5524 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1106-5

3.1 Clock Generator
XIN; XOUT - Crystal In; Crystal Out.
3.2 Control Pins and Serial Data I/O
CS - Chip Select.
SDI - Serial Data Input.
SDO - Serial Data Output.
SCLK - Serial Clock Input.
A0, A1 - Logic Outputs.
3.3 Measurement and Reference Inputs
AIN1+, AIN1-, AIN2+, AIN2- AIN3+, AIN3-, AIN4+, AIN4- - Differential Analog Input.
AIN1+, AIN2+, AIN3+, AIN4+, AIN5+, AIN6+, AIN7+, AIN8+ - Single-Ended Analog Input.
VREF+, VREF- - Voltage Reference Input.
DS317F4
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device.
When active low, the port will recognize SCLK. When high the SDO pin will output a high
impedance state. CS should be changed when SCLK = 0.
SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK.
A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins
respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin
will recognize clocks only when CS is low.
The logic states of A0-A1 mimic the states of the D22/D10-D23/D11 bits of the channel-setup
register. Logic Output 0 = AGND, and Logic Output 1 = VA+.
Differential input pins into the CS5522 and CS5524 devices.
Single-ended input pins into the CS5528.
Fully differential inputs which establish the voltage reference for the on-chip modulator.
SDO is the serial data output. It will output a high impedance state if CS = 1.
CS5521/22/23/24/28
49