CS5524-ASZ Cirrus Logic Inc, CS5524-ASZ Datasheet - Page 36
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CS5524-ASZ
Manufacturer Part Number
CS5524-ASZ
Description
IC ADC 24BIT 4CH 20SSOP
Manufacturer
Cirrus Logic Inc
Specifications of CS5524-ASZ
Number Of Converters
1
Package / Case
24-SSOP
Number Of Bits
24
Data Interface
Serial
Power Dissipation (max)
14.8mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Adc Inputs
4
Architecture
Delta-Sigma
Conversion Rate
617 SPs
Resolution
24 bit
Input Type
Voltage
Interface Type
Serial (3-Wire)
Voltage Reference
2.5 V
Supply Voltage (max)
5 V
Supply Voltage (min)
25 mV
Maximum Power Dissipation
500 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Input Voltage
25 mV to 5 V
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1012 - EVAL BOARD FOR CS5524 ADC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1106-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS5524-ASZ
Manufacturer:
CIRRUS
Quantity:
20 000
SDO line.
"00000000" is provided on SDI, the converter will
remain in this conversion mode, and continue to
perform conversions on the selected Setup. To exit
this conversion mode, "11111111" must be provid-
ed on SDI during the first 8 SCLKs. If the user de-
cides to exit, 24 more SCLKs are required to read
the final conversion word from the data register and
return to command mode.
2.4.1.3 Repeated One-Setup Conversions with
Wait
(LP = 1 MC = 0 RC = 1)
In this conversion mode, the ADC will repeatedly
perform conversions, referencing only one Setup.
The 8-bit command word contains the CSRP bits,
which instruct the converter which Setup to use
when performing the conversion. Note that in this
mode, every conversion word must be read. The
part will wait for the current conversion word to be
read before performing the next conversion.
To perform repeated, one-Setup conversions with
wait, the MC bit must be set to '0', the LP bit must
be set to '1', and the RC bit must be set to '1' in the
Configuration Register. Then, the 8-bit command
word that references the desired Setup must be sent
to the converter. The ADC will then begin per-
forming conversions on the referenced Setup, and
SDO will fall to indicate when a conversion is com-
plete, and data is available. Thirty-two SCLKs are
then needed to read the conversion word from the
data register. The first 8 SCLKs are used to clear
the SDO flag. During the last 24 SCLKs, the data
word will be output from the converter on the SDO
line. If, during the first 8 SCLKs, "00000000" is
provided on SDI, the converter will remain in this
conversion mode, and continue to perform conver-
sions on the selected Setup after each data word is
read. To exit this conversion mode, "1111 1111"
must be provided on SDI during the first 8 SCLKs.
If the user decides to exit, 24 more SCLKs are re-
36
If, during the first 8 SCLKs,
quired to read the final conversion word from the
data register and return to command mode.
2.4.1.4 Single, Multiple-Setup Conversions
(LP = 0 MC = 1 RC = X)
In this conversion mode, the ADC will perform sin-
gle conversions, referencing multiple Setups, and
return to command mode after the data for all con-
versions have been read. The CSRP bits in the
command word are ignored in this mode. Instead,
the Depth Pointer (DP3-DP0) bits in the Configu-
ration Register are accessed to determine the num-
ber of Setups to reference when collecting the data.
The number of Setups referenced will be equal to
(DP3-DP0) + 1, and will be accessed in order, be-
ginning with Setup1.
To perform single, multiple-Setup conversions, the
MC bit must be set to '1', and the LP bit must be set
to '0' in the Configuration Register. Then, the 8-bit
command word to start a conversion must be sent
to the converter. Because the CSRP bits of the
command word are ignored in this mode, a "start
convert" command referencing any of the available
Setups will begin the conversions. The ADC will
then perform conversions using the appropriate
number of Setups (as dictated by the DP bits in the
Configuration Register), beginning with Setup1.
The SDO line will fall after the final conversion to
indicate that the data is ready. Eight SCLKs, plus
24 SCLKs for each Setup referenced are required to
read the conversion words from the data FIFO. The
first 8 SCLKs are used to clear the SDO flag. Ev-
ery 24 bits thereafter consist of the data words of
each Setup that was referenced, until all of the data
has been read from the part. The data word from
Setup1 is output first, followed by the data word
from Setup2, and so on for the appropriate number
of Setups. The part returns to command mode im-
mediately after the final data word has been read,
and waits for the next command to be issued.
CS5521/22/23/24/28
DS317F4