ISL51002CQZ-150 Intersil, ISL51002CQZ-150 Datasheet - Page 20

• Manufacturer Part Number: ISL51002CQZ-150
• Description: IC FRONT END 10BIT VID 128-MQFP
• Manufacturer: Intersil

Specifications of ISL51002CQZ-150

• Number Of Bits: 10
• Number Of Channels: 3
• Power (watts): 1.2W
• Voltage - Supply, Analog: 1.8V, 3.3V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Listing
0x52
0x53
0x54
0x55
ADDRESS
Phase ADJ MASK V, (0x01)
Horizontal pixel mask 1,
(0x01)
Horizontal pixel mask 2,
(0x01)
Phase Adjust Command
Options, (0x20)
(DEFAULT VALUE)
REGISTER
(Continued)
20
BITS
2:0
6:4
7:0
7:0
3
0
1
2
3
4
5
6
7
PADJ Exclude v2
N/A
PADJ
PADJ Exclude h1
PADJ Exclude h2
PADJ Blue Disable
PADJ Green Disable
PADJ Red Disable
PADJ Adjust Search Option Search option for auto phase adjustment
PADJ Adjust Speed
Update Phase on VSYNC
PADJ Soft Reset
Reserved
FUNCTION NAME
E
xclude v1
ISL51002
Vertical line mask: How many lines to exclude before the
leading edge of VSYNC
000: 0 lines
001: 1 lines (default)
010: 2 lines
011: 4 lines
100: 6 lines
101: 8 lines
110: 10 lines
111: 12 lines
Choose how many lines to exclude after the leading edge of
VSYNC (typically used to exclude VBI data)
000: 5 lines (default)
001: 18 lines
010: 19 lines (480i)
011: 20 lines (1080i)
100: 22 lines (576i)
101: 25 lines (720p)
110: 41 lines (480p/1080p)
111: 44 lines (576p)
If a value of ‘N’ is programmed in this register, 2*N pixels after
the active edge of HS
collection.
Must be >0 for proper operation.
If a value of ‘N’ is programmed in this register, 2*N pixels
before the active edge of HS
collection.
Must be >0 for proper operation.
Enable/disable blue color for measurement
0: enable
1: disable
Enable/disable green color for measurement
0: enable
1: disable
Enable/disable red color for measurement
0: enable
1: disable
0: best phase
1: worst phase
This is a hidden bit for customers. It decides whether the
search steps are 28 (fast) or 64 VSYNC intervals (slow).
0: 28 VSYNCs
1: 64 VSYNCs
0: phase updated immediately
1: phase updated on VSYNC (default)
0: Normal operation
1: Reset all phase adjust state machines
Set to 0
Take high then low to reset phase adjust block
OUT
DESCRIPTION
will be excluded from data
OUT
will be excluded from data
September 19, 2007
FN6164.2