isl51002-150 Intersil Corporation, isl51002-150 Datasheet

Page 1

... Automatic Black Level Compensation (ABLC™) eliminates part-to-part offset variation, ensuring perfect black level performance in every application. The ISL51002's Digital PLL generates a pixel clock from the analog source's HSYNC or SOG (Sync-On-Green) signals. Pixel clock output frequencies range from 10MHz to 165MHz with sampling clock jitter of 250ps peak to peak ...

Page 2

... Ordering Information PART NUMBER/PART MARKING ISL51002CQZ-110 (Note) ISL51002CQZ-150 (Note) ISL51002CQZ-165 (Note) ISL51002EVALZ NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...

Page 3

... JA 2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside. JC Electrical Specifications Specifications apply for V pixel rate = 110MHz for ISL51002-110, 150MHz for ISL51002-150, 165MHz for ISL51002-165, f and T A SYMBOL PARAMETER FULL CHANNEL CHARACTERISTICS Conversion Rate ...

Page 4

... Electrical Specifications Specifications apply for V pixel rate = 110MHz for ISL51002-110, 150MHz for ISL51002-150, 165MHz for ISL51002-165, f and T A SYMBOL PARAMETER Input Capacitance Full Power Bandwidth SOG INPUT CHARACTERISTICS (SOG Sync Tip Clamp SOG Pull Down V /V Input Threshold Voltage IH IL (relative to bottom of sync tip) ...

Page 5

... Electrical Specifications Specifications apply for V pixel rate = 110MHz for ISL51002-110, 150MHz for ISL51002-150, 165MHz for ISL51002-165, f and T A SYMBOL PARAMETER I Analog Supply Current, 1.8V A1.8 (Note 4) I Digital Supply Current, 3.3V D3.3 (Note 4) I Digital Supply Current, 1.8V D1.8 (Note 4) IADC D1.8 IPLL D1.8 P Total Power Dissipation D AC TIMING CHARACTERISTICS ...

Page 6

... YUV Output Data Timing and Latency HSYNC IN ANALOG VIDEO IN DATACLK G[9:0] R[9:0] B[9:0] HS OUT 6 ISL51002 t HOLD t SETUP THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED TO. THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST OF THE AFE’S OUTPUT SIGNALS ...

Page 7

... Pin Configuration (MQFP, ISL51002 A1 GND SOG A3 GND VREF RED A1.8 13 SOG GND ISL51002CQZ-xxx GND VREF GREEN 21 SOG ...

Page 8

... HSYNC pattern. This is typically used for measuring VSYNC period. 8 ISL51002 DESCRIPTION . A signal, aligned with the digital pixel data Take low for at least 1µs and then high again to reset the ISL51002. This D centered around 0.5V. P-P centered around 0.5V. P /2. May be used as system clock for other system ...

Page 9

... Power supply for the digital PLL section. Connect to a 1.8V supply and bypass to GND D1.8 GND Ground return for V D ATEST1, 2 For production use only. Tie to GND DTEST1 For production use only. Tie to GND NC Reserved. Do not connect anything to these pins. 9 ISL51002 DESCRIPTION , V , and VPLL . A3.3 A1.8 A1 VADC , and VPLL . ...

Page 10

Sync Flow 3 CH0 3 165 MHZ CH1 3 TRIPLE 10- BIT 3 CH2 AFE 3 CH3 SOG SOG0 SLICER A SOG1 SOG2 SOG SOG3 SLICER B HSYNC HSYNC0 SLICER A HSYNC1 HSYNC2 HSYNC HSYNC3 SLICER B VSYNC VSYNC0 SLICER ...

Page 11

... Characteristics, (read only) 0x02 CH0 and CH1 Activity Status, (read only) 0x03 CH2 and CH3 Activity Status, (read only) 11 ISL51002 BITS FUNCTION NAME 1:0 SYNC Type 00: Automatic Sync Selection logic could not find good sync SOG (Automatic Sync mode only) 01: SYNC on HSYNC/VSYNC ...

Page 12

... ADDRESS (DEFAULT VALUE) 0x04 Interrupt Status, Write each bit to clear it, 0xFF to clear all. 0x05 Interrupt Mask Register, (0xFF) 12 ISL51002 BITS FUNCTION NAME 0 CH0 Sync Changed 0: No change 1: CH0 activity or polarity changed 1 CH1 Sync Changed 0: No change 1: CH1 activity or polarity changed ...

Page 13

... Green Gain LSB, (0x00) 0x16 Blue Gain MSB, (0x55) 0x17 Blue Gain LSB, (0x00) 0x18 Red Offset MSB, (0x80) 13 ISL51002 BITS FUNCTION NAME 1:0 Input Channel Select Sets video muxes as well as HSYNC, VSYNC, and SOG input muxes. 0: CH0 1: CH1 2: CH2 (single-ended mode only) ...

Page 14

... DC Restore and ABLC starting pixel MSB, (0x00) 0x25 DC Restore and ABLC starting pixel LSB, (0x02) 0x26 DC Restore Clamp Width, (0x10) 14 ISL51002 BITS FUNCTION NAME 5:0 N/A 7:6 Red Offset LSB 2 LSBs of 10-bit offset word 7:0 Green Offset MSB ABLC off: upper 8-bits to Green offset DAC ...

Page 15

... REGISTER ADDRESS (DEFAULT VALUE) 0x27 ABLC Configuration, (0x40) 0x28 Output Format 1, (0x00) 15 ISL51002 BITS FUNCTION NAME 0 ABLC Disable 0: ABLC on (default) - use 10-bit digital offset control. 0x000 = -0x200 LSB offset, 0x3FF = +0x1FF LSB offset, 0x200 = 0x000 LSB offset 1: ABLC off - use 10-bit offset DACs, bypass digital adder ...

Page 16

... Output Signal Disable, (0xFF) Note: All digital outputs are tristated by default to ease multiplexing with other AFEs 0x2C Power Control, (0x00) 16 ISL51002 BITS FUNCTION NAME 0 DATACLK Polarity 0: Pixel data changes on falling edge (default) 1: Pixel data changes on rising edge 1 FIELD output polarity 0: Odd = low, Even = high (default) ...

Page 17

... All values referred to voltage at HSYNC input pin, 300mV hysteresis 0x30 SOG Slicer Thresholds, (0x66) 17 ISL51002 BITS FUNCTION NAME 4:0 Crystal Clock Frequency Crystal clock frequency in MHz (decimal). 0x00: Test Mode, Do not use. 0x01 through 0x0A: 10MHz, APLL DIV = 35 (0x23) 0x0B: 11MHz, APLL DIV = 32 ...

Page 18

... HSYNC Period LSB, (read only) 0x42 HSYNC Width MSB, (read only) 0x43 HSYNC Width LSB, (read only) 18 ISL51002 BITS FUNCTION NAME 3:0 Glitch Filter Width 0: 16 crystal clocks 1: 17 crystal clocks 2: 1 crystal clocks 3: 2 crystal clocks 4: 3 crystal clocks (default) ...

Page 19

... AUTO ADJUST REGISTERS 0x50 Phase ADJ CMD FN, (0x00) 0x51 Phase ADJ STATUS, (read only) 19 ISL51002 BITS FUNCTION NAME 3:0 VSYNC Period MSB These bits report a 12-bit value containing the width of one frame (= 2 fields for interlaced field for progressive) of video. VSYNC period for measured channel = ...

Page 20

... Horizontal pixel mask 1, (0x01) 0x54 Horizontal pixel mask 2, (0x01) 0x55 Phase Adjust Command Options, (0x20) 20 ISL51002 BITS FUNCTION NAME 2:0 PADJ Exclude v2 Vertical line mask: How many lines to exclude before the leading edge of VSYNC 000: 0 lines 001: 1 lines (default) 010: 2 lines ...

Page 21

... Phase Adjust Data 0, (read only) 0x60 AFE CTRL, (0x00) 0x61 ADC CTRL, (0x00) 21 ISL51002 BITS FUNCTION NAME 7:0 PADJ Threshold Threshold of transitions visible for capturing. These are the 8 MSBs of the 10-bit threshold word used for phase quality measurements. The actual 10-bit threshold used equals the value in this register times 4 ...

Page 22

... So precision, low-jitter sampling is a fundamental requirement at these speeds, and a difficult one for an analog PLL to meet. The ISL51002's DPLL has less than 250ps of jitter, peak to peak, and independent of the pixel rate. The DPLL generates 64 phase steps per pixel (vs. the industry standard 32), for fine, accurate positioning of the sampling point ...

Page 23

... The range for each color is typically 0V to 0.7V from black to white. HSYNC and VSYNC are separate signals. Component YPbPr Inputs In addition to RGB and RGB with SOG, the ISL51002 has an option that is compatible with the component YPbPr video inputs typically generated by DVD players. While the ISL51002 digitizes signals in these color spaces, it can only perform color space conversion from RGB to YUV ...

Page 24

... SOG triggers. The SOG threshold sets the comparator threshold relative to the sync tip (the bottom of the SOG pulse). Inside the ISL51002, a 1µA pulldown ensures that each sync tip triggersthe clamp circuit causing the tip to be clamped to a 600mV level. A comparator compares the SOG signal with an internal 4-bit programmable threshold level reference ranging from 0mV to 300mV above the sync clamp level ...

Page 25

... SYNC Timing Measurement The ISL51002 analyzes the timing characteristics of the sysnc signals for the currently selected input channel and presents the results in registers 0x40 through 0x0x46. The HSYNC period and pulse width values are 16-bit ...

Page 26

... Sampling Phase to the best setting. Set register 0x50 to 0x03 to activate the auto phase adjust function. Data Enable (DE) Generator The ISL51002 provides a signal that is high during the active video time when properly configured. This signal is used by devices such as DVI/HDMI transmitters to gate the active portion of the video and ignore the H and V sync times ...

Page 27

... SOG signal, while non-standard SOG signals and TriLevel sync signals may have amplitudes below the default SOG slicer levels and not be easily detected consequence, not all of the activity detect bits in the ISL51002 are correct under all conditions. For best SOG operation, the SOG low pass filter (register 0x04[4] should always be enabled to reject the high frequency peaking often seen on video signals ...

Page 28

... The ISL51002 has a 7-bit address on the serial bus. The upper 6-bits are permanently set to 100110, with the lower bit determined by the state of pin 67. This allows two ISL51002s to be independently controlled while sharing the same bus ...

Page 29

... Data on the serial bus must be valid for the entire time SCL is high (Figure 5). To achieve this, data being written to the ISL51002 is latched on a delayed version of the rising edge of SCL. SCL is delayed and deglitched inside the ISL51002 for three crystal clock periods (120ns for a 25MHz crystal) to eliminate spurious clock pulses that could disrupt serial communication ...

Page 30

... ISL51002 FIGURE 6. CONFIGURATION REGISTER WRITE 30 ISL51002 Signals the beginning of serial I/O R/W ISL51002 Serial Bus Address Write This is the 7-bit address of the ISL51002 on the 2-wire bus. The A address is 0x98 if pin 67 is low, 0x9A if pin 67 is high. Shift this PIN 67) value left to when adding the R/W bit. ...

Page 31

... This sets the initial address of the ISL51002’s configuration register for subsequent reading. Ends the previous transaction and starts a new one R/W ISL51002 Serial Bus Address Write This is the 7-bit address of the ISL51002 on the 2-wire bus. The A address is 0x98 if pin 67 is low, 0x9A if pin 67 is high. R (PIN 67) indicating next transaction(s) will be a read ...

Page 32

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 32 ISL51002 MDP0055 14x20mm 128 LEAD MQFP (WITH AND WITHOUT HEAT SPREADER) 3.2mm FOOTPRINT ...