ISL51002CQZ-150 Intersil, ISL51002CQZ-150 Datasheet - Page 16

• Manufacturer Part Number: ISL51002CQZ-150
• Description: IC FRONT END 10BIT VID 128-MQFP
• Manufacturer: Intersil

Specifications of ISL51002CQZ-150

• Number Of Bits: 10
• Number Of Channels: 3
• Power (watts): 1.2W
• Voltage - Supply, Analog: 1.8V, 3.3V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Listing
0x29
0x2A
0x2B
0x2C
ADDRESS
Output Format 2, (0x00)
HS
Output Signal Disable,
(0xFF)
Note: All digital outputs are
tristated by default to ease
multiplexing with other
AFEs
Power Control, (0x00)
OUT
(DEFAULT VALUE)
Width, (0x10)
REGISTER
(Continued)
16
BITS
7:0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
DATACLK Polarity
FIELD output polarity
Macrovision
HS
HS
XTALCLKOUT Frequency
Enable XTALCLKOUT
HS
Tri-state Red
Tri-state Green
Tri-state Blue
Tri-state SYNC
Tri-state DATACLK
Tri-state DATACLKb
Tri-state DE
Tri-state Field
Red Power Down
Green Power Down
Blue Power Down
PLL Power Down
OUT
OUT
OUT
FUNCTION NAME
Polarity
Lock Edge
Width
ISL51002
0: Pixel data changes on falling edge (default)
1: Pixel data changes on rising edge
0: Odd = low, Even = high (default)
1: Odd = high, Even = low
0: Digitize Macrovision encoded signals (default)
1: Blank AFE output for Macrovision encoded signals. If
0: Active High (default)
1: Active Low
0: HS
1: HS
0: XTALCLKOUT= f
1: XTALCLKOUT= f
0 = XTALCLKOUT is logic low (default)
1 = XTALCLKOUT enabled
HS
determines whether leading or trailing edge is locked to
HSYNC
0 = Outputs enabled
1 = Outputs in tri-state
0 = Outputs enabled
1 = Outputs in tri-state
0 = Outputs enabled
1 = Outputs in tri-state
0 = HS
1 = Outputs in tri-state
0 = Output enabled
1 = Output in tri-state
0 = Output enabled
1 = Output in tri-state
0 = Output enabled
1 = Output in tri-state
0 = Output enabled
1 = Output in tri-state
0 = Red ADC operational (default)
1 = Red ADC powered down
0 = Green ADC operational (default)
1 = Green ADC powered down
0 = Blue ADC operational (default)
1 = Blue ADC powered down
0 = PLL operational (default)
1 = PLL powered down
Macrovision is detected, AFE output is always 0x00 0x00
0x00 for RGB, or 0x00, 0x80, 0x80 for YUV.
lockedge. Trailing edge moves forward in time as HSOUT
width is increased (default).
lockedge. Leading edge moves backward in time as
HS
OUT
OUT
OUT
OUT
OUT
IN
Width in pixels, 0x00 to 0xFF. HS
’s leading edge is locked to selected HSYNC
’s trailing edge is locked to selected HSYNC
width is increased.
, HSYNC
CRYSTAL
CRYSTAL
OUT
DESCRIPTION
, VSYNC
/2
(default)
OUT
enabled
OUT
Lock Edge
September 19, 2007
IN
FN6164.2
IN
’s
’s