PCA2125TS/1,112 NXP Semiconductors, PCA2125TS/1,112 Datasheet - Page 17

• Manufacturer Part Number: PCA2125TS/1,112
• Description: IC CMOS RTC/CALENDAR 14-TSSOP
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCA2125TS/1,112

• Package / Case: 14-TSSOP
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Function: Clock, Calendar
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.3 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6292 - DEMO BOARD PCA2125 RTC
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283386112; PCA2125TS/1; PCA2125TS/1

NXP Semiconductors
PCA2125_1
Product data sheet
8.6.3 Timer flags
8.7 Interrupt output
When reading the timer, the current countdown value is returned and not the initial
value n. For accurate read back of the countdown value, the SPI-bus clock (SCL) must be
operating at a frequency of at least twice the selected timer clock. Since it is not possible
to freeze the countdown timer counter during read back, it is recommended to read the
register twice and check for consistent results.
When a minute or second interrupt occurs, bit MSF is set to logic 1. Similarly, at the end of
a timer countdown, bit TF is set to logic 1. These bits maintain their value until overwritten
by software. If both countdown timer and minute/second interrupts are required in the
application, the source of the interrupt can be determined by reading these bits. To
prevent one flag being overwritten while clearing another, a logic AND is performed during
a write access. The flag is reset by writing a logic 0 but its value is not affected by writing a
logic 1.
Three examples are given for clearing the flags. Flags MSF and TF are cleared by a write
command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values.
Repeatedly re-writing these bits has no influence on the functional behavior.
Table 30.
Table
appropriate flag.
Table 31.
Table 32.
Table 33.
Clearing the alarm flag (bit AF) operates in exactly the same way; see
An active LOW interrupt signal is available at pin INT. Operation is controlled via the bits
of control register 2. Interrupts can be sourced from three places: second/minute timer,
countdown timer and alarm function.
Bit TI_TP configures the timer generated interrupts to be either a pulse or to follow the
status of the interrupt flags (bits TF and MSF).
Register
Control_2
Register
Control_2
Register
Control_2
Register
Control_2
31,
Table 32
Flag location in register Control_2
Example to clear only TF (bit 2) in register Control_2
Example to clear only MSF (bit 5) in register Control_2
Example to clear both TF and MSF (bits 2 and 5) in register Control_2
Bit 7
-
Bit 7
-
Bit 7
-
Bit 7
-
and
Table 33
Rev. 01 — 28 July 2008
Bit 6
-
Bit 6
-
Bit 6
-
Bit 6
-
show what instruction must be sent to clear the
Bit 5
MSF
Bit 5
1
Bit 5
0
Bit 5
0
Bit 4
-
Bit 4
-
Bit 4
-
Bit 4
-
Bit 3
AF
Bit 3
1
Bit 3
1
Bit 3
1
SPI Real-time clock/calendar
Bit 2
TF
Bit 2
0
Bit 2
1
Bit 2
0
PCA2125
Section
© NXP B.V. 2008. All rights reserved.
Bit 1
-
Bit 1
-
Bit 1
-
Bit 1
-
8.5.1.
Bit 0
-
Bit 0
-
Bit 0
-
Bit 0
-
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