M41ST87WMX6TR STMicroelectronics, M41ST87WMX6TR Datasheet
M41ST87WMX6TR
Specifications of M41ST87WMX6TR
M41ST87WMX6TR
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M41ST87WMX6TR Summary of contents
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V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM Features ■ 5.0, 3.3, or 3.0 V operation 2 ■ 400 kHz I C bus ■ NVRAM supervisor to non-volatize ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M41ST87Y, M41ST87W 3.1 TIMEKEEPER 3.2 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M41ST87Y, M41ST87W List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The M41ST87Y/W serial TIMEKEEPER CMOS SRAM organized as 160 bytes by 8 bits. A built-in 32.768 kHz oscillator (internal crystal-controlled) and 8 bytes of the SRAM (see function and are configured in binary coded decimal (BCD) format. ...
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M41ST87Y, M41ST87W Figure 1. Logic diagram 1. Open drain output 2. Programmable output (open drain or full-CMOS) Figure 2. 28-pin, 300 mil SOIC (MX) connections Note: No function (NF) and no connect (NC) pins should be tied to V internally ...
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Description Table 1. Signal names E CON EX (1) IRQ/OUT PFI 1 PFI 2 (2) PFO 1 (2) PFO 2 (1) RST RSTIN1 RSTIN2 SCL SDA (2) SQW/FT WDI OUT V SS (1) F 32k TP1 IN ...
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M41ST87Y, M41ST87W Figure 3. Block diagram SDA INTERFACE SCL Crystal OSCILLATOR V OUT WDI 2 TPX BAT V SS RSTIN1 RSTIN2 EX PFI 1 1.25V (Internal) PFI 2 1.25V (Internal) 1. Open drain output. 2. Programmable ...
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Description Figure 4. Hardware hookup Inhibit Unregulated V Voltage IN 5V Regulator Inhibit V IN 3.3V Regulator For monitoring of additional voltage sources Pushbutton 10/48 M41ST87Y TP1 IN TP2 ...
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M41ST87Y, M41ST87W 2 Operating modes The M41ST87Y/W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 160 bytes contained in the device can ...
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Operating modes 2.1 2-wire bus characteristics The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to ...
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M41ST87Y, M41ST87W case the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 5. Serial bus data transfer sequence CLOCK DATA START CONDITION Figure 6. Acknowledgement sequence START SCL FROM MASTER DATA ...
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Operating modes Table 2. AC characteristics Symbol f SCL clock frequency SCL t Time the bus must be free before a new transmission can start BUF propagation delay EXPD CON t SDA and SCL fall time ...
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M41ST87Y, M41ST87W Figure 8. Slave address location START Figure 9. READ mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS DATA n+X Figure 10. Alternate READ mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ...
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Operating modes 2.3 WRITE mode In this mode the master transmitter transmits to the M41ST87Y/W slave receiver. Bus protocol is shown in (R/W=0) is placed on the bus and indicates to the addressed device that word address An will follow ...
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M41ST87Y, M41ST87W power input is switched from the V SRAM are maintained from the attached battery supply. All outputs become high impedance. The V M41ST87W) or 150µA (for M41ST87Y) of current to the attached memory with less than 0.3 volts ...
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Operating modes 2.6.2 Tamper bits (TB1 and TB2) If the TEB bit is set, and a tamper condition occurs, the TB X “Read-only” and is reset only by setting the TEB register 0Fh. 2.6.3 Tamper interrupt enable bits (TIE1 and ...
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M41ST87Y, M41ST87W Figure 13. Tamper detect connection options I. NORMALLY OPEN (TCM III. V OUT ( NORMALLY TCHI/TCLO = 1 CLOSED (TCM Note: These options are connected to those ...
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Operating modes Figure 14. Tamper detect output options User Configuration TP1 TEB1 TP2 TEB2 Figure 15. Basic tamper detect options OUT TCM , TPM = 1 OUT TCM , TPM = 0,0 ...
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M41ST87Y, M41ST87W 2.6.6 Tamper detect sampling (TDS1 and TDS2) This bit selects between a 1Hz sampling rate or constant monitoring of the tamper input pin(s) to detect a tamper event when the normally closed switch mode is selected. This allows ...
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Operating modes the output of the inverting charge pump and the V should be an enhancement mode p-channel, and placed between V and V of the external SRAM. When TP CC n-channel MOSFET will turn on and the p-channel will ...
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M41ST87Y, M41ST87W Figure 17. Tamper current options OUT TAMPER HI, NORMALLY OPEN OUT TAMPER LO, TCHI/TCLO = 1 NORMALLY CLOSED TAMPER LO, NORMALLY OPEN TCHI/TCLO = 1 TAMPER HI, NORMALLY CLOSED Figure ...
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Operating modes Table 5. Tamper detect timing Symbol Parameter (1) t Tamper RAM clear ext delay CLRD t Tamper clear timing CLR 1. With input capacitance = 70 pF and resistance = the OF bit is set, ...
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M41ST87Y, M41ST87W tamper connect mode bit (TCM the tamper pin will be triggered by being connected (if the TPM CC X external switch is closed, the tamper bit will be immediately set, allowing the user to determine ...
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Operating modes 2.10 Avoiding inadvertent tampers (normally closed configuration) In some applications it may be necessary to use a low pass filter to reduce electrical noise on the tamper input pin when the TCM the tamper detect switch is located ...
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M41ST87Y, M41ST87W 2.11 Tamper event time-stamp Regardless of which tamper occurs first, not only will the appropriate tamper bit be set, but the event will also be automatically time-stamped. This is accomplished by freezing the normal update of the clock ...
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Clock operation 3 Clock operation The eight byte clock register (see read the date and time from the clock binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Note: ...
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M41ST87Y, M41ST87W 3.1 TIMEKEEPER The M41ST87Y/W offers 22 internal registers which contain clock, control, alarm, watchdog, flag, square wave, and tamper data. The clock registers are memory locations which contain external (user accessible) and internal copies of the data (usually ...
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Clock operation Keys Must be set to zero 32kE = 32 kHz output enable bit ABE = Alarm in battery backup mode enable bit RS0-RS3 = SQW frequency AF = Alarm flag (read only) AFE = Alarm flag ...
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M41ST87Y, M41ST87W adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to ...
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Clock operation Figure 22. Calibration waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION 3.3 Setting alarm clock registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, ...
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M41ST87Y, M41ST87W Figure 23. Alarm interrupt reset waveform 0Eh ACTIVE FLAG IRQ/OUT Table 8. Alarm repeat modes RPT5 RPT4 Figure 24. Backup mode alarm waveform ...
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Clock operation 3.4 Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. Bits BMB4-BMB0 store a binary ...
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M41ST87Y, M41ST87W Table 9. Square wave output frequency RS3 3.6 Full-time 32 kHz square wave output The M41ST87Y/W offers the user a special 32kHz ...
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Clock operation t will not generate a reset condition. RSTIN1 and RSTIN2 are each internally pulled through a 100 k resistor. CC Figure 25. RSTIN1 & RSTIN2 timing waveforms RSTIN1 RSTIN2 RST Table 10. Reset AC ...
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M41ST87Y, M41ST87W output will be configured as open drain (with I PFOD is set to '0,' the outputs will be configured as full-CMOS (sink and source current as specified in Table 17 on page Note: When configured as open drain ...
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Clock operation 3.14 t bit rec Bit D7 of clock register 04h contains the t of the deselect time after V WRITEs may again be performed to the device after a power-down condition. The t allow the user to set ...
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M41ST87Y, M41ST87W Table 12. t definitions rec t bit (TR) rec Default setting Table 13. Default values Condition Initial power-up Subsequent power-up (with (2)(3) battery backup) Condition Initial power-up Subsequent power-up (with (2)(3) battery backup) Condition ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 14. ...
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M41ST87Y, M41ST87W 5 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests ...
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DC and AC parameters Table 17. DC characteristics Sym Parameter Test condition Battery current T = 25°C, V OSC ON A (2) I BAT Battery current OSC OFF I Supply current CC1 Supply current I SCL, SDA = V CC2 ...
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M41ST87Y, M41ST87W 4. Outputs deselected. 5. External SRAM must match RTC supervisor chip V 6. For rechargeable backup, V (max) may be considered V BAT 7. For PFO and PFO (if PFOD = '0'), SQW/FT (if SQWOD = '0'), and ...
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DC and AC parameters Table 18. Power down/up AC characteristics Symbol ( (max PFD PFD ( (min PFD before power down ...
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M41ST87Y, M41ST87W 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. ECOPACK is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings ...
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Part numbering 7 Part numbering Table 20. Ordering information scheme Example: Device type M41ST Supply voltage and write protect voltage 87Y = V = 4. THS bit = '1': 4. 4.5 to 5.5 ...
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M41ST87Y, M41ST87W 8 Revision history Table 21. Document revision history Date Revision May-2002 23-Apr-2003 10-Jul-2003 11-Sep-2003 15-Jun-2004 7-Sep-2004 29-Jun-2005 28-Mar-2006 10-Sep-2008 1 First issue. 2 Document promoted to Preliminary Data. 2.1 Update tamper information ( Update electrical, charge pump, and ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...