SI5325C-B-GM Silicon Laboratories Inc, SI5325C-B-GM Datasheet
SI5325C-B-GM
Specifications of SI5325C-B-GM
Related parts for SI5325C-B-GM
SI5325C-B-GM Summary of contents
Page 1
Description The Si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5325 accepts dual clock inputs ranging from 10 to ...
Page 2
Si5325 Table 1. Performance Specifications (V = 1.8, 2.5, or 3.3 V ±10 – º Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F ...
Page 3
Table 1. Performance Specifications (Continued 1.8, 2.5, or 3.3 V ±10 – º Parameter Symbol Rise/Fall Time CKO TRF Duty Cycle CKO DC PLL Performance Jitter Generation J GEN Jitter Transfer J ...
Page 4
Si5325 130 Ω 82 Ω Input Clock Sources* 130 Ω 82 Ω Control Mode (L) Reset Figure 1. Si5325 Typical Application Circuit (I2C Control Mode 3 ...
Page 5
Functional Description The Si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5325 accepts dual clock inputs ranging from 10 to 710 MHz and generates two independent, synchronous clock outputs ranging ...
Page 6
Si5325 2. Pin Descriptions: Si5325 INT_C1B VDD GND GND Pin numbers are preliminary and subject to change. Pin # Pin Name I RST 14, NC — 18, 19, 20, 30 INT_C1B O Note: ...
Page 7
Table 3. Si5325 Pin Descriptions (Continued) Pin # Pin Name I/O 4 C2B O 5, 10 GND GND 12 CKIN2 CKIN2– 16 CKIN1 CKIN1– 21 CS_CA ...
Page 8
Si5325 Table 3. Si5325 Pin Descriptions (Continued) Pin # Pin Name I/O 22 SCL I 23 SDA_SDO I A2_SS I 27 SDI I 29 CKOUT1– CKOUT1+ 34 CKOUT2– CKOUT2+ 36 ...
Page 9
... Ordering Guide Ordering Part Output Clock Frequency Number Si5325A-B-GM 970–1134 MHz 1.213–1.417 GHz Si5325B-B-GM Si5325C-B-GM Package Range 10–945 MHz 36-Lead QFN 10–808 MHz 36-Lead QFN 10–346 MHz 36-Lead QFN Preliminary Rev. 0.26 Si5325 Temperature Range – °C – °C – ...
Page 10
Si5325 4. Package Outline: 36-Pin QFN Figure 3 illustrates the package details for the Si5325. Table 4 lists the values for the dimensions shown in the illustration. Figure 3. 36-Pin Quad Flat No-lead (QFN) Symbol Millimeters Min Nom A 0.80 ...
Page 11
Recommended PCB Layout Figure 4. PCB Land Pattern Diagram Preliminary Rev. 0.26 Si5325 11 ...
Page 12
Si5325 Table 5. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI ...
Page 13
OCUMENT HANGE IST Revision 0.23 to Revision 0.24 Clarified that the two outputs have a common, higher frequency source on page 1. Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on page 3. Added Figure ...
Page 14
... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...