IDT5V9885BPFGI IDT, Integrated Device Technology Inc, IDT5V9885BPFGI Datasheet
IDT5V9885BPFGI
Specifications of IDT5V9885BPFGI
Available stocks
Related parts for IDT5V9885BPFGI
IDT5V9885BPFGI Summary of contents
Page 1
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR FEATURES: • Three internal PLLs • Internal non-volatile EEPROM • JTAG and FAST mode serial interfaces • Input Frequency Ranges: 1MHz to 400MHz • Output Frequency Ranges: 4.9kHz to 500MHz • ...
Page 2
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR FUNCTIONAL BLOCK DIAGRAM XTALOUT OSC. XTALIN/REFIN CLKIN SHUTDOWN/OE GIN5/CLK_SEL Multi-Purpose I/O, Programming, Features 2 I C/JTAG NOTE: 1. OUT4 and OUT5 pairs can be configured to be LVDS, LVPECL, or two single-ended LVTTL outputs. ...
Page 3
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR PIN CONFIGURATION CLKIN 1 GND 2 GOUT1/LOSS_CLKIN 3 XTALIN/REFIN 4 XTALOUT 5 OUT1 OUT3 TQFP TOP VIEW ...
Page 4
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR PIN DESCRIPTION PF32 NL28 Pin Name Pin# Pin# CLKIN 1 XTALIN/REFIN 4 XTALOUT 5 GIN0/SDAT/TDI 19 GIN1/SCLK/TCK 20 GIN2/TMS 24 GIN3/SUSPEND 27 GIN4/TRST 25 GIN5/CLK_SEL 21 SHUTDOWN/ C/JTAG 22 2 OUT1 6 ...
Page 5
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR PLL FEATURES AND DESCRIPTIONS D0 Divider VCO M0 Multiplier PLL0 Block Diagram D1 Divider VCO M1 Multiplier PLL1 Block Diagram D2 Divider VCO M2 Multiplier PLL2 Block Diagram 5 INDUSTRIAL TEMPERATURE RANGE Spread Spectrum ...
Page 6
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Pre-Divider (D) Values PLL0 1 - 255 PLL1 1 - 255 PLL2 1 - 255 REFERENCE CLOCK INPUT PINS AND SELECTION The 5V9885B supports up to two clock inputs. One of the clock inputs ...
Page 7
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Feedback-Divider N[11:0] and A[3:0] are the bits used to program the feedback-divider for PLL0 (N0 and A0) and PLL1 (N1 and A1). If spread spectrum generation is enabled for either PLL0 or PLL1, then ...
Page 8
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Note that the actual 10-bit post-divider value has a 2 added to the integer value Q and the outputs are routed through another div/2 block. The post-divider should never be disabled unless the output ...
Page 9
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Modulation frequency (Eq. 11) PFD (Eq. 12) VCO PFD NOM Nssc * Tssc) (Eq. 13) SSC PFD ...
Page 10
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Example F = 25MHz 100MHz, Fssc = 33KHz with center spread of ±2%. Find the necessary spread spectrum register settings. IN OUT Since the spread is center, the SS_OFFSET can be set ...
Page 11
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR The spread spectrum parameters such as the modulation frequency and profile will not be enabled nor will it have any impact on the PLL output when the PLL is programmed for fractional divide. The ...
Page 12
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR LOOP FILTER The loop filter for each PLL can be programmed to optimize the jitter performance. The low-pass frequency response of the PLL is the mechanism that dictates the jitter transfer characteristics. The loop ...
Page 13
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR To determine if the loop is stable, the phase margin (ωm) would need to be calculated as follows. Phase Margin: ω (Rz * Cz) (Eq. 23) ω ...
Page 14
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR CONFIGURING THE MULTI-PURPOSE I/Os The 5V9885B can operate in four distinct modes. These modes are controlled by the MFC bit (0x04) and the I (GIN0, GIN1, GIN2, GIN3, GIN4, GIN5) have different uses depending ...
Page 15
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR MODE2 - Manual Frequency Control (MFC=0) Mode for all PLLs In this mode, the configuration of PLL0, PLL1, and PLL2 can be changed during operation. The GINx pins are used to control the selection ...
Page 16
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Understanding the GIN Signals During power up, the part will virtually be in MFC mode2, therefore, the values of GIN4, GIN3, GIN2, GIN1 and GIN0 will be latched and used for PLL configuration selection, ...
Page 17
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR MANUAL FREQUENCY CONTROL (MFC) BLOCK DIAGRAM PLL0 Prescaler "D" CONFIG0 CONFIG1 CONFIG2 CONFIG3 Multiplier "M" CONFIG0 CONFIG1 CONFIG2 CONFIG3 PLL1 Prescaler "D" CONFIG0 CONFIG1 CONFIG2 CONFIG3 Multiplier "M" CONFIG0 CONFIG1 CONFIG2 CONFIG3 PLL2 Prescaler ...
Page 18
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR MANUAL FREQUENCY CONTROL (MFC) BLOCK DIAGRAM PLL0 Prescaler "D" CONFIG0 CONFIG1 CONFIG2 CONFIG3 Multiplier "M" CONFIG0 CONFIG1 CONFIG2 CONFIG3 PLL1 Prescaler "D" CONFIG0 CONFIG4 CONFIG5 Multiplier "M" CONFIG0 CONFIG4 CONFIG5 PLL2 Prescaler "D" CONFIG0 ...
Page 19
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR BLOCK DIAGRAM FOR SHUTDOWN/OE CONTROL SIGNAL MUX SHUTDOWN/OE NOTE: This illustration shows the internal logic behind the SHUTDOWN/OE pin and the bits associated with it. PM2 OE1 ...
Page 20
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR POWER UP AND POWER SAVING FEATURES If a global shutdown is enabled, SHUTDOWN pin asserted, most of the chip except for the PLLs will be powered down. In order to have a complete power ...
Page 21
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Revertive The input clock selection will switch to the secondary clock source when there are no transitions on the primary clock source for two secondary clock cycles. LOSS_LOCK and LOSS_CLKIN signals will be asserted. ...
Page 22
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR PROGRAMMING THE DEVICE I C and JTAG may be used to program the 5V9885B. The LOW for I C mode. 2 Hardwired Parameters for the IDT5V9885B JTAG identification number = ...
Page 23
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR EXTERNAL I C INTERFACE CONDITION 2 KEY: From Master to Slave From Master to Slave, but can be omitted if followed by the correct sequence ...
Page 24
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR PROGSAVE S Address R/W ACK Command Code ACK 7-bits 0 1-bit 8-bits:xxxxxx01 NOTE: PROGWRITE is for writing to the 5V9885B registers. PROGREAD is for reading the 5V9885B registers. PROGSAVE is for saving all the ...
Page 25
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR In order for the save and restore instructions to function properly, the IDT5V9885B must not be in shutdown mode (SHUTDOWN pin asserted). In the event of an interrupt of some sort such as a ...
Page 26
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR I C BUS DC CHARACTERISTICS 2 Symbol Parameter V Input HIGH Level IH V Input LOW Level IL V Hysteresis of Inputs HYS I Input Leakage Current IN V Output LOW Voltage OL I ...
Page 27
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Symbol Description V Internal Power Supply Voltage DD V Input Voltage I (2) V Output Voltage O T Junction Temperature J T Storage Temperature STG NOTE: 1. Stresses greater than those ...
Page 28
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter V Input HIGH Voltage Level (1) IHH V Input MID Voltage Level (1) IMM V Input LOW Voltage Level (1) ILL I 3-Level Input DC Current ...
Page 29
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR DC ELECTRICAL CHARACTERISTICS FOR LVDS Symbol Parameter V (+) Differential Output Voltage for the TRUE binary state OT V (-) Differential Output Voltage for the FALSE binary state OT ∆ V Change in V ...
Page 30
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR AC TIMING ELECTRICAL CHARACTERISTICS (SPREAD SPECTRUM GENERATION = OFF) Symbol Parameter f Input Frequency IN 1/t1 Output Frequency f VCO Frequency VCO f PFD Frequency PFD f Loop Bandwidth BW t2 Input Duty Cycle ...
Page 31
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR TEST CIRCUITS AND CONDITIONS V DD 0.1µF NOTE: 1. All V pins must be tied together. DD OTHER TERMINATION SCHEME (BLOCK DIAGRAM) OUTPUTS GND LVTTL: -15pF for each output OUTPUTS GND LVPECL ...
Page 32
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR RAM (PROGRAMMING REGISTER) TABLES BIT # (Default Settings) Default Register ADDR Hex Value 0x00 0x01 0x02 0x03 ...
Page 33
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR RAM (PROGRAMMING REGISTER) TABLES BIT # (Default Settings) Default Register ADDR Hex Value OEM1[1; 0x1F 0 ...
Page 34
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR RAM (PROGRAMMING REGISTER) TABLES BIT # (Default Settings) Default ADDR Register 7 Hex Value 0x40 0 0 ...
Page 35
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR RAM (PROGRAMMING REGISTER) TABLES BIT # (Default Settings) Default ADDR Register 7 Hex Value 0x60 0 0 ...
Page 36
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR RECOMMENDED LANDING PATTERN NOTE: All dimensions are in millimeters. INDUSTRIAL TEMPERATURE RANGE NL 28 pin 36 ...
Page 37
IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR ORDERING INFORMATION XXXXX XX X IDT Package Process Device Type CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 INDUSTRIAL TEMPERATURE RANGE Industrial (-40°C to +85°C) I Thin Quad Flat Pack - ...