CY28RS400ZXCT Cypress Semiconductor Corp, CY28RS400ZXCT Datasheet - Page 10

• Manufacturer Part Number: CY28RS400ZXCT
• Description: IC CLOCK GENERATOR 56-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generatorr

Specifications of CY28RS400ZXCT

• Frequency - Max: 100MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP II
• Frequency-max: 100MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output: -
• Input: -

Document #: 38-07637 Rev. *B
CPU_STP# Assertion
The CPU_STP# signal is an active low input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final states of the stopped CPU signals are
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is 2 - 6 CPU clock cycles.
CPUC Internal
CPUT Internal
CPU_STP#
CPU_STP#
CPUT
CPUC
CPUT
CPUC
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
USB, 48MHz
PCI, 33MHz
DOT96C
DOT96T
REF
Figure 4. Power-down Deassertion Timing Waveform
PD
Figure 6. CPU_STP# Deassertion Waveform
Figure 5. CPU_STP# Assertion Waveform
Tdrive_CPU_STP#,10nS>200mV
<300µS, >200mV
Tdrive_PWRDN#
Tstable
<1.8nS
CPUT = HIGH and CPUC = LOW. There is no change to the
output drive current values during the stopped state. The
CPUT is driven HIGH with a current value equal to 6 x (Iref),
and the CPUC signal will be Hi-Z. When the control register
CPU_STP Hi-Z bit corresponding to the output of interest is
programmed to ‘1’, the final state of the stopped CPU clock is
low (due to external 50 ohm pull-down resistor), both CPUT
clock and CPUC clock outputs will not be driven.
CY28RS400
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