IDT82V3280DQG8 IDT, Integrated Device Technology Inc, IDT82V3280DQG8 Datasheet - Page 128
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IDT82V3280DQG8
Manufacturer Part Number
IDT82V3280DQG8
Description
IC PLL WAN SE STRATUM 2 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of IDT82V3280DQG8
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
622.08MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3280DQG8
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PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Configuration *
Programming Information
IDT82V3280
Address: 5BH
Type: Read / Write
Default Value: 10XXX010
FINE_PH_LOS_
5 - 3
2 - 0
LIMT_EN
Bit
7
6
7
FINE_PH_LOS_LIMT_EN
PH_LOS_FINE_LIMT[2:0]
FAST_LOS_SW
FAST_LOS_SW
Name
-
6
Reserved.
This bit controls whether the occurrence of the fine phase loss will result in the T0/T4 DPLL unlocked.
0: Disabled.
1: Enabled. (default)
The value in this bit can be switched only when it is available for T0 path; this bit is always ‘1’ when it is available for T4
path.
This bit controls whether the occurrence of the fast loss will result in the T0/T4 DPLL unlocked.
0: Does not result in the T0 DPLL unlocked. T0 DPLL will enter Temp-Holdover mode automatically. (default)
1: Results in the T0/T4 DPLL unlocked. For T0 path, T0 DPLL will enter Lost-Phase mode if the T0 DPLL operating
mode is switched automatically.
These bits set a fine phase limit.
000: 0.
001: ± (45 ° ~ 90 °).
010: ± (90 ° ~ 180 °). (default)
011: ± (180 ° ~ 360 °).
100: ± (20 ns ~ 25 ns).
101: ± (60 ns ~ 65 ns).
110: ± (120 ns ~ 125 ns).
111: ± (950 ns ~ 955 ns).
5
-
4
-
128
3
-
Description
PH_LOS_FINE
_LIMT2
2
PH_LOS_FINE
_LIMT1
1
December 9, 2008
PH_LOS_FINE
_LIMT0
0
WAN PLL
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