SY89538LHG TR Micrel Inc, SY89538LHG TR Datasheet - Page 6

• Manufacturer Part Number: SY89538LHG TR
• Description: IC SYNTHESIZR LVPECL/LVDS 64TQFP
• Manufacturer: Micrel Inc
• Series: Precision Edge®r
• Type: Clock Synthesizer/Fanout Bufferr

Specifications of SY89538LHG TR

• Pll: Yes
• Input: CMOS, HSTL, LVDS, LVPECL, LVTTL, SSTL, Crystal
• Output: LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:7
• Differential - Input:output: Yes/Yes
• Frequency - Max: 756MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Frequency-max: 756MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SY89538LHGTR; SY89538LHGTR

Pin Description
Input/Output
Input Driver Select Table
Pre-Divider Frequency Select Table
June 2006
Pin Number
54, 61, 64
32, 48,
11, 12
17, 18
20, 21
49, 50
52, 53
38, 39
41, 42
44, 45
3, 4
8, 9
POUT0, /POUT0
POUT1, /POUT1
POUT2, /POUT2
POUT3, /POUT3
LOUT0, /LOUT0
LOUT1, /LOUT1
LOUT2, /LOUT2
XTAL2, XTAL1
RFCK, /RFCK
RSEL1
FBIN, /FBIN
Pin Name
Table 1. Reference Input Divider and Zero-Delay MUX Divider Select Table
0
0
1
1
NC
PDSEL1
0
0
1
1
RSEL0
Pin Function
External Feedback Input used as the zero delay input. Output feeds into the inputs to
configure the device in zero-delay mode, which forces the output frequency to the
same frequency of the RFCK frequency. Requires external termination. See “Zero
Delay FBIN Input” section for more details.
Reference Clock Differential Input. Input accepts any input, single-ended or
differential: TTL/CMOS, LVPECL, LVDS, HSTL, and SSTL. RFCK requires an
external termination. See “Input Interface” and “Input Termination” sections for more
details.
Crystal Input. Directly connect a series resonant crystal across inputs. See “Quartz
Crystal Oscillator Specification” table. Place crystal as close to the input as possible,
keep XTAL and traces away from adjacent noisy traces to minimize noise coupling,
and place the XTAL on the same side as the SY89538L (component side).
100K LVPECL Output Drivers. Terminate all LVPECL outputs with 50Ω to V
Each output pair has a respective output frequency control (PSELx, PENx, DSEL).
See “LVPECL Output Post-Divider and Frequency Select Table” for proper decoding.
For low-jitter applications, unused LVPECL output pairs should be terminated with
pull-down resistors. See “Output Termination Recommendations” section for
termination detail.
Differential LVDS-Compatible Output Drivers. Output termination is 100Ω across the
pair. For low-jitter applications, unused LVDS output pairs should be terminated with
100Ω across the pair. See “Output Termination Recommendations” section for
details.
No connect.
0
1
0
1
Table 2. Pre-Divider Select Table
PDSEL0
0
1
0
1
Internal Reference
6
RFCK / 8
RFCK / 4
RFCK / 2
RFCK / 1
Clock
Pre-Div-Out Frequency
(VCO/2) / 5
(VCO/2) / 4
(VCO/2) / 3
(VCO/2) / 2
[e-mail]
MUX Divider
Zero-Delay
FBIN / 8
FBIN / 4
FBIN / 2
FBIN / 1
or [phone]
M9999-062706-D
CCO
–2V.