MPC9992AC IDT, Integrated Device Technology Inc, MPC9992AC Datasheet - Page 8

• Manufacturer Part Number: MPC9992AC
• Description: IC PLL CLK GEN ECL/PECL 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9992AC

• Pll: Yes with Bypass
• Input: PECL, Crystal
• Output: PECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:7
• Differential - Input:output: Yes/Yes
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
8
Power Supply Filtering
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the V
characteristics, for instance I/O jitter. The MPC9992 provides
separate power supplies for the output buffers (V
phase-locked loop (V
this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the
V
power supply filter scheme. The MPC9992 frequency and
phase stability is most susceptible to noise with spectral
content in the 100 kHz to 20 MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop across the series filter resistor R
the I
pin) is typically 9 mA (12 mA maximum), assuming that a
minimum of 2.955 V must be maintained on the V
The resistor R
10-15 Ω to meet the voltage drop criteria.
MPC9992
CC_PLL
The MPC9992 is a mixed analog/digital product. Its analog
CC_PLL
CC_PLL
pin for the MPC9992.
current (the current sourced through the V
F
Differential Pulse
shown in
power supply impacts the device
Generator
Z = 50 Ω
CC_PLL
Figure 4
) of the device. The purpose of
Figure 4
must have a resistance of
V
Z = 50 Ω
TT
F
. From the data sheet
R
T
illustrates a typical
= 50 Ω
Figure 5. MPC9992 AC Test Reference
CC
CC_PLL
) and the
CC_PLL
pin.
MPC9992 DUT
8
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in
3-5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9992 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
The minimum values for R
As the noise frequency crosses the series resonant point
V
CC
Figure 4. V
Z = 50 Ω
Figure
R
R
F
T
= 10 – 15Ω
= 50 Ω
R
4, the filter cut-off frequency is around
CC_PLL
F
Advanced Clock Drivers Device Data
C
F
F
33...100 nF
Power Supply Filter
and the filter capacitor C
C
F
= 22 µF
10 nF
Freescale Semiconductor
V
TT
V
V
CC_PLL
CC
MPC9992
F
NETCOM
are
MPC9992