MPC9992AC IDT, Integrated Device Technology Inc, MPC9992AC Datasheet - Page 3

• Manufacturer Part Number: MPC9992AC
• Description: IC PLL CLK GEN ECL/PECL 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9992AC

• Pll: Yes with Bypass
• Input: PECL, Crystal
• Output: PECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:7
• Differential - Input:output: Yes/Yes
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
Advanced Clock Drivers Device Data
Freescale Semiconductor
Table 1. MPC9992 PLL Configurations
Table 2. Function Table (Configuration Controls)
Table 3. Pin Configuration
REF_SEL
VCO_SEL
PLL_EN
MR/STOP
PCLK, PCLK
XTAL_IN, XTAL_OUT
VCO_SEL
PLL_EN
REF_SEL
MR/STOP
FSEL[1:0]
QA[0-3], QA[0–3]
QB[0-2], QB[0–2]
QSYNC, QSYNC
GND
V
V
VCO_SEL
CC
CC_PLL
Control
0
0
0
0
1
1
1
1
Pin
FSEL_0
Default
0
0
1
1
0
0
1
1
VCO_SEL and FSEL[1:0] control the operating PLL frequency range and input/output frequency ratios.
1
1
1
0
Input
Input
Input
Input
Input
Input
Output
Output
Output
Supply
Supply
Supply
Selects PCLK, PCLK as PLL references signal input
Selects VCO÷2. The VCO frequency is scaled by a factor
of 2 (high input frequency range)
Test mode with the PLL bypassed. The reference clock is
substituted for the internal VCO output. MPC9992 is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
Normal operation
I/O
FSEL_1
0
1
0
1
0
1
0
1
PECL
Analog
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PECL
PECL
PECL
GND
V
V
CC
CC
Type
f
16.6–33.3
16.6–33.3
REF
8.3–16.6
8.3–16.6
12.5–25
See Table 1 for the device frequency configuration.
25–50
10–20
5–10
(MHz)
Differential reference clock signal input
Crystal oscillator interface
VCO operating frequency select
PLL Enable/Bypass mode select
PLL reference signal input select
Device reset and output clock disable (stop in logic low state)
Output and PLL feedback frequency divider select
Differential clock outputs (bank A)
Differential clock outputs (bank B)
Differential clock outputs (bank C)
Negative power supply
Positive power supply. All V
correct DC and AC operation
PLL positive power supply (analog power supply). It is recommended to use an external RC
filter for the analog power supply pin V
0
QA[3:0] (N
(10 ⋅ f
(12 ⋅ f
(10 ⋅ f
(12 ⋅ f
(6 ⋅ f
(8 ⋅ f
VCO÷16
(6 ⋅ f
(8 ⋅ f
VCO÷16
VCO÷8
VCO÷4
VCO÷8
VCO÷4
VCO÷8
VCO÷8
REF
REF
REF
REF
REF
REF
REF
REF
)
)
)
)
3
)
)
)
)
A
)
QB[2:0] (N
CC
(4 ⋅ f
(4 ⋅ f
(4 ⋅ f
(4 ⋅ f
(4 ⋅ f
(4 ⋅ f
(4 ⋅ f
(4 ⋅ f
VCO÷12
VCO÷20
VCO÷12
VCO÷24
VCO÷16
VCO÷40
VCO÷24
VCO÷8
pins must be connected to the positive power supply for
REF
REF
REF
REF
REF
REF
REF
REF
Selects the crystal oscillator as PLL reference signal
input
Selects VCO÷4. The VCO frequency is scaled by a factor
of 4 (low input frequency range).
Normal operation mode with PLL enabled.
Reset of the device and output disable (output clock
stop). The outputs are stopped in logic low state: Qx=L,
Qx=H. The minimum reset period should be greater than
one reference clock cycle.
)
)
)
)
)
)
)
)
B
)
CC_PLL
Function
Frequency Ratio
. Please see applications section for details
QA to QB
3÷2
2÷1
5÷2
3÷1
3÷2
2÷1
5÷2
3÷1
1
Internal Feedback
(M ⋅ VCO_SEL)
VCO÷160
VCO÷48
VCO÷32
VCO÷80
VCO÷48
VCO÷96
VCO÷64
VCO÷96
MPC9992
NETCOM
3
MPC9992