ICS84330AV-02LF IDT, Integrated Device Technology Inc, ICS84330AV-02LF Datasheet - Page 8

• Manufacturer Part Number: ICS84330AV-02LF
• Description: IC SYNTHESIZER 700MHZ 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Frequency Synthesizerr

Specifications of ICS84330AV-02LF

• Pll: Yes
• Input: LVCMOS, LVTTL, Crystal
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: No/Yes
• Frequency - Max: 700MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 84330AV-02LF

P
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84330-02 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V
T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
84330AV-02
RTT =
ERMINATION FOR
OWER
((V
F
S
FOUT
OH
IGURE
UPPLY
+ V
OL
3A. LVPECL O
) / (V
1
F
ILTERING
LVPECL O
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
T
Z
ECHNIQUES
o
50Ω
UTPUT
UTPUTS
A
T
RTT
ERMINATION
CCA
50Ω
PPLICATION
pin.
V
CC
CC
FIN
- 2V
and V
www.idt.com
D
CCA
IFFERENTIAL
8
I
NFORMATION
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
700MH
FOUT
F
IGURE
LVPECL F
F
IGURE
Z
, L
3B. LVPECL O
2. P
OW
Z
Z
V
o
o
V
CCA
= 50Ω
= 50Ω
CC
OWER
J
ITTER
REQUENCY
125Ω
84Ω
.01μF
.01μF
S
UPPLY
ICS84330-02
UTPUT
, C
3.3V
3.3V
RYSTAL
F
10Ω
10μF
125Ω
84Ω
T
ILTERING
ERMINATION
S
YNTHESIZER
REV. B JULY 25, 2010
FIN
-
TO
-3.3V