ICS84330AV-02LF IDT, Integrated Device Technology Inc, ICS84330AV-02LF Datasheet - Page 2

• Manufacturer Part Number: ICS84330AV-02LF
• Description: IC SYNTHESIZER 700MHZ 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Frequency Synthesizerr

Specifications of ICS84330AV-02LF

• Pll: Yes
• Input: LVCMOS, LVTTL, Crystal
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: No/Yes
• Frequency - Max: 700MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 84330AV-02LF

F
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 6, NOTE 1.
The ICS84330-02 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A quartz crystal is used as the input to the on-chip
oscillator. The output of the oscillator is divided by 16 prior to
the phase detector. With a 16MHz crystal this provides a 1MHz
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be 2M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS84330-02 support two
input modes to program the M divider and N output divider. The
two input operational modes are parallel and serial. Figure 1
shows the timing diagram for each mode. In parallel mode the
nP_LOAD input is LOW. The data on inputs M0 through M8 and
N0 through N1 is passed directly to the M divider and N output
NOTE: nP_LOAD is designed to eliminate runt pulses when changing M and N bits.
84330AV-02
M0:M8, N0:N1
UNCTIONAL
S_CLOCK
nP_LOAD
nP_LOAD
S_LOAD
S_LOAD
S_DATA
D
ESCRIPTION
T2
0
0
0
0
1
1
1
1
T1
0
0
1
1
0
0
1
1
t
S
T2
F
t
IGURE
H
T0
0
1
0
1
0
1
0
1
T1
1. P
(S_CLOCK ÷ M) /2 (non 50% Duty Cycle M divider)
(VCO ÷ M) /2 (non 50% Duty Cycle M divider)
T0
t
M, N
S
ARALLEL
LVCMOS Output Frequency < 200MHz
N1
t
H
www.idt.com
D
Time
N0
P
IFFERENTIAL
& S
S
PLL Reference Xtal ÷ 16
TEST Output
ARALLEL
ERIAL
2
Shift Register Out
ERIAL
divider. On the LOW-to-HIGH transition of the nP_LOAD input,
the data is latched and the M divider remains loaded until the
next LOW transition on nP_LOAD or until a serial event occurs.
The TEST output is Mode 000 (shift register out) when operat-
ing in the parallel input mode. The relationship between the VCO
frequency, the crystal frequency and the M divider is defined as
follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 125 ≤ M ≤ 350. The frequency out is defined as
follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider when S_LOAD tran-
sitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD.
If S_LOAD is held HIGH, data at the S_DATA input is passed
directly to the M divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and
test bits T2:T0. The internal registers T2:T0 determine the state
of the TEST output as follows:
M8
700MH
L
fOUT ÷ 4
OADING
fOUT
M7
L
L
High
Low
OAD
OADING
fVCO =
fout = fVCO =
M6
LVPECL F
O
PERATIONS
Z
, L
N
fxtal x
16
M5
OW
M4
fxtal x
2M
16
J
ITTER
M3
REQUENCY
2M
N
ICS84330-02
M2
, C
S_CLOCK ÷ N divider
RYSTAL
M1
S
M0
YNTHESIZER
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
REV. B JULY 25, 2010
t
-
S
TO
-3.3V