IDT74FCT88915TT70PY IDT, Integrated Device Technology Inc, IDT74FCT88915TT70PY Datasheet - Page 5

• Manufacturer Part Number: IDT74FCT88915TT70PY
• Description: IC PLL CLK GENERATOR 28-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 74FCTr
• Type: Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of IDT74FCT88915TT70PY

• Pll: Yes with Bypass
• Input: LVTTL
• Output: LVCMOS, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 70MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Frequency-max: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 74FCT88915TT70PY

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, C
5. t
6. With V
7. These two specs ( t
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
t
All Outputs
t
2Q Output
t
Q, Q, Q/2 Outputs
t
2Q Output
t
2Q Output
t
SYNC-FEEDBACK
t
(rising)
t
(falling)
t
t
t
Reset – Q
t
t
PD
SKEWr
LOCK (6)
RST
REC (10)
W (10)
RISE/FALL
RISE/FALL
PULSE WIDTH
PULSE WIDTH
PULSE WIDTH
SKEWf
SKEW
capacitor shown in Figure 2).
by IDT, the termination scheme shown in Figure 1 must be used:
CYCLE
Symbol
ALL
(3, 4)
(3, 4)
CC
= 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
(3, 4)
(3)
(3)
(3)
fully powered-on and an output properly connected to the FEEDBACK pin. t
(3)
RISE/FALL
(3)
Rise/Fall Time
(between 0.2 V
Rise/Fall Time
(between 0.8V and 2.0V)
Output Pulse Width
Q0-Q4, Q5, Q/2 @ V
Output Pulse Width
2Q Output @ V
Output Pulse Width
2Q @ 1.5V
SYNC input to FEEDBACK delay
(measured at SYNC0 or 1 and FEEDBACK
input pins)
Output to Output Skew between outputs 2Q,
Q0-Q4,Q/2 (rising edges only)
Output to Output Skew between outputs 2Q,
Q0-Q4 (falling edges only)
Output to Output Skew
2Q, Q/2, Q0-Q4 rising, Q5 falling
Time required to acquire Phase-Lock from time
SYNC input signal is received
Propagation Delay, RST (HIGH-to-LOW) to any
Output (HIGH-to-LOW)
Reset Recovery Time
Rising RST edge to falling SYNC edge
Minimum Pulse Width RST input LOW
and t
88915TT
L
Output
PULSE WIDTH
= 50pF (±2pF), and at a fixed temperature and voltage.
2Q
Parameter
CC
CC
/2
and 0.8 V
2Q output) guarantee that the FCT88915TT meets 68040 P-Clock input specification. For these two specs to be guaranteed
CC
Figure 1. MC68040 P-Clock Input Termination Scheme
/2
CC
Rs = Zo - 7
)
Rs
Ω
Zo (clock trace)
0.1MF from LF to Analog GND
Load = 50Ω to V
5
LOCK
Termination as in
C
Condition
termination
R
C
C
C
C
C
L
Max. is with C1 = 0.1µF, t
L
L
L
L
L
L
= 20pF &
note 7
= 500Ω
= 50pF
= 50pF
= 50pF
= 20pF
= 50pF
Rp
(1)
(7)
CC
/2,
(9)
Rp = 1.5 Zo
LOCK
0.5t
0.5t
0.5t
P-Clock
COMMERCIAL TEMPERATURE RANGE
CYCLE
CYCLE
Min. is with C1 = 0.01µF (where C1 is loop filter
68040
CYCLE
Input
0.5
1.5
Min.
–0.5
1
1
—
—
—
9
5
(2)
(2)
(2)
(2)
– 0.5
– 0.5
– 1
(5)
(5)
(5)
0.5t
0.5t
0.5t
CYCLE
CYCLE
CYCLE
Max.
+0.5
500
500
500
2.5
1.6
10
—
—
8
+ 0.5
+ 0.5
+ 1
(5)
(5)
(5)
Unit
ms
ns
ns
ns
ns
ns
ns
ps
ps
ps
ns
ns
ns