IDT74FCT88915TT70PY IDT, Integrated Device Technology Inc, IDT74FCT88915TT70PY Datasheet

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IDT74FCT88915TT70PY

Manufacturer Part Number
IDT74FCT88915TT70PY
Description
IC PLL CLK GENERATOR 28-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
74FCTr
Type
Fanout Distribution, Multiplexer , Zero Delay Bufferr
Datasheet

Specifications of IDT74FCT88915TT70PY

Pll
Yes with Bypass
Input
LVTTL
Output
LVCMOS, LVTTL
Number Of Circuits
1
Ratio - Input:output
2:8
Differential - Input:output
No/No
Frequency - Max
70MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
*
Frequency-max
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
74FCT88915TT70PY
FEATURES:
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
• Max. output frequency: 133MHz
• Pin and function compatible with MC88915
• Five non-inverting outputs, one inverting output, one 2x
• Output Skew < 500ps (max.)
• Duty cycle distortion < 500ps (max.)
• Part-to-part skew: 0.55ns (from t
• 64/–15mA drive at TTL output voltage levels
• Available in PLCC and SSOP packages
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
© 2001 Integrated Device Technology, Inc.
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
(FREQ_SEL = HIGH)
output, one ÷2 output; all outputs are TTL-compatible
FEEDBAC K
FREQ_SEL
REF_SEL
SYNC (0)
SYNC (1)
PLL_EN
RST
0
1
M
u
x
PD
max. spec)
LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
Phase/Freq.
Detector
0
Divide
-By-2
Mux
1
(
(
÷
÷
1)
2)
1
DESCRIPTION:
and phase of outputs to the input reference clock. It provides low skew clock
distribution for high performance PCs and workstations. One of the outputs is
fed back to the PLL at the FEEDBACK input resulting in essentially zero delay
across the device. The PLL consists of the phase/frequency detector, charge
pump, loop filter and VCO. The VCO is designed to run optimally between
20MHz and f2Q Max.
inverted from the Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs
at half the Q frequency.
PLL _EN allows bypassing of the PLL, which is useful in static test modes. When
PLL_EN is low, SYNC input may be used as a test clock. In this test mode, the
input frequency is not limited to the specified range and the polarity of outputs
is complementary to that in normal operation (PLL_EN = 1). The LOCK output
attains logic high when the PLL is in steady-state phase and frequency lock.
mended in Figure 2.
C harge Pump
The FCT88915TT uses phase-lock loop technology to lock the frequency
The FCT88915TT provides eight outputs with 500ps skew. The Q5 output is
The FREQ_SEL control provides an additional ÷ 2 option in the output path.
The FCT88915TT requires external loop filter components as recom-
1
0
M
u
x
CP
CP
CP
D
D
D
CP
CP
CP
CP
D
CP
D
D
D
D
COMMERCIAL TEMPERATURE RANGE
R
R
R
R
R
R
R
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Controlled
Oscilator
Voltage
IDT74FCT88915TT
55/70/100/133
MARCH 2001
LOCK
LF
2Q
Q0
Q1
Q2
Q3
Q4
Q5
Q/2
DSC-4245/4

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IDT74FCT88915TT70PY Summary of contents

Page 1

IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER FEATURES: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec (FREQ_SEL = HIGH) • Max. output frequency: 133MHz • Pin and function compatible with MC88915 • Five non-inverting ...

Page 2

IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER PIN CONFIGURATIONS FEEDBK 5 REF_SEL 6 SYNC( (AN GND(AN) 11 SYNC( PLCC TOP VIEW PIN DESCRIPTION Pin Name I/O ...

Page 3

IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER ABSOLUTE MAXIMUM RATINGS Symbol Description V (2) Terminal Voltage with Respect to GND TERM V (3) Terminal Voltage with Respect to GND TERM T Operating Temperature A T Temperature Under Bias BIAS T ...

Page 4

IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER POWER SUPPLY CHARACTERISTICS Symbol Parameter ΔI Quiescent Power Supply Current CC TTL Inputs HIGH I Dynamic Power Supply CCD (4) Current C Power Dissipation Capacitance PD (5,6) I Total Power Supply Current C ...

Page 5

IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter t Rise/Fall Time RISE/FALL All Outputs (between 0.2 V and 0 Rise/Fall Time RISE/FALL (3) 2Q Output (between 0.8V and 2.0V) t Output ...

Page 6

IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER GENERAL AC SPECIFICATION NOTES, CONTINUED 8. The wiring diagrams and written explanations of Figures 4a-4c demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable SYNC input range to ...

Page 7

IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER μ μ 0.1 F Low High Freq. Freq. Bypass Bypass Figure 3. Recommended Loop Filter and Analog Isloation Scheme for the FCT88915TT NOTES: 1. Figure 3 shows a loop filter and ...

Page 8

IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER The frequency relationship shown here is applicable to all Q outputs (Q0, Q1, Q2, Q3 and Q4). 1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q/2 output is connected to ...

Page 9

IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER CLOCK @ f SYSTEM CLOCK SOURCE DISTRIBUTE CLOCK @ f CLOCK @ 2f at point of use Figure 5. Multiprocessing Application Using the FCT88915 for Frequency Multiplication FCT88915 SYSTEM LEVEL TESTING FUNCTIONALITY When ...

Page 10

IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER TEST CIRCUITS AND WAVEFORMS Pulse D.U.T. Generator R T Test Circuits For All Outputs SYNC IN PUT (SYNC (1) or SYNC (0)) FEED BACK INPUT Q/2 OUTPUT t ...

Page 11

IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER ORDERING INFORMATION IDT XX FCT XXXX Temp. Range Device Type NOTE: 1. When ordering GREEN packages, replace this numeric value with the equivalent letter below MHz B= 70 MHz C= 100 ...

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