MPC961CAC IDT, Integrated Device Technology Inc, MPC961CAC Datasheet - Page 6

• Manufacturer Part Number: MPC961CAC
• Description: IC BUFFER ZD 1:18 PLL 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of MPC961CAC

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:17
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MPC961C Data Sheet
MPC961C REVISION 5 AUGUST 17, 2009
reflection coefficient, to 2.62 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in this
case 4.0 ns).
any false clock triggering, however designers may be uncomfortable
with unwanted reflections on the line. To better match the
impedances when driving multiple lines the situation in
should be used. In this case the series terminating resistors are
reduced such that when the parallel combination is added to the
output buffer impedance the line impedance is perfectly matched.
engineers who want to simulate their specific interconnect schemes.
At the load end the voltage will double, due to the near unity
Since this step is well above the threshold region it will not cause
SPICE level and IBIS output buffer models are available for
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 6. Optimized Dual Line Termination
V
Z
R
R
V
Figure 5. Single versus Dual Waveforms
O
L
L
S
O
MPC961
t
D
2
Output
Buffer
14Ω
14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω
= V
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 14 Ω
= 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31 V
= 3.8956
OutA
In
S
(Z
4
O
/ (R
25 Ω = 25 Ω
R
R
6
S
S
S
= 22 Ω
= 22 Ω
Time (ns)
+ R
t
D
= 3.9386
OutB
O
8
+ Z
O
Z
Z
O
O
))
10
= 50 Ω
= 50 Ω
12
Figure 6
14
6
Using the MPC961C in Zero-Delay Applications
Designs using the MPC961C as LVCMOS PLL fanout buffer with
zero insertion delay will show significantly lower clock skew than
clock distributions developed from CMOS fanout buffers. The
external feedback option of the MPC961C clock driver allows for its
use as a zero delay buffer. By using the QFB output as a feedback
to the PLL the propagation delay through the device is virtually
eliminated. The PLL aligns the feedback clock output edge with the
clock input reference edge resulting a near zero delay through the
device. The maximum insertion delay of the device in zero-delay
applications is measured between the reference clock input and any
output. This effective delay consists of the static phase offset, I/O
jitter (phase or long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Calculation of Part-to-Part Skew
critical clock signal timing can be maintained across several
devices. If the reference clock inputs of two or more MPC961C are
connected together, the maximum overall timing uncertainty from
the common CCLK input to any output is:
phase offset, output skew, feedback board trace delay and I/O
(phase) jitter:
specified. I/O jitter numbers for other confidence factors (CF) can be
derived from
Nested clock trees are typical applications for the MPC961C.
The MPC961C zero delay buffer supports applications where
This maximum timing uncertainty consist of 4 components: static
Due to the statistical nature of I/O jitter a rms value (1 σ) is
Any Q
Any Q
TCLK
QFB
QFB
Max. skew
Figure 7. MPC961C Max. Device-to-Device Skew
Common
Device 1
Device 1
Device 2
Device2
t
SK(PP)
Table
= t
(∅)
8.
+ t
t
JIT(∅)
SK(O)
—t
+t
(∅)
SK(O)
+ t
©2009 Integrated Device Technology, Inc.
+t
LOW VOLTAGE ZERO DELAY BUFFER
PD, LINE(FB)
(∅)
t
JIT(∅)
t
SK(PP)
t
PD,LINE(FB)
+t
+ t
SK(O)
JIT(∅)
· CF