ICS87946AYI-01LF IDT, Integrated Device Technology Inc, ICS87946AYI-01LF Datasheet - Page 5

IC CLOCK GENERATOR 32-LQFP

ICS87946AYI-01LF

Manufacturer Part Number
ICS87946AYI-01LF
Description
IC CLOCK GENERATOR 32-LQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Clock Generatorr
Datasheet

Specifications of ICS87946AYI-01LF

Pll
No
Input
CML, LVPECL, SSTL
Output
LVCMOS, LVTTL
Number Of Circuits
1
Ratio - Input:output
1:10
Differential - Input:output
Yes/No
Frequency - Max
250MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
250MHz
Number Of Clock Inputs
1
Mode Of Operation
Differential
Output Logic Level
LVCMOS/LVTTL
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
LQFP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
87946AYI-01LF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS87946AYI-01LF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ICS87946AYI-01LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
AC Electrical Characteristics
Table 5A. AC Characteristics, V
NOTE 1: Measured from the differential input crossing point to V
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load
conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at V
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, V
For NOTES, please see Table 5A above.
IDT™ / ICS™ 16:1, SINGLE-ENDED MULTIPLEXER
Parameter Symbol
f
t
tsk(b)
tsk(o)
tsk(w)
tsk(pp)
tjit
t
odc
t
t
Parameter Symbol
f
t
tsk(b)
tsk(o)
tsk(w)
tsk(pp)
tjit
t
odc
t
t
MAX
PD
R
EN
DIS
MAX
PD
R
EN
DIS
ICS87946I-01
LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
/ t
/ t
F
F
Output Frequency
Propagation Delay; NOTE 1
Bank Skew, NOTE 2, 7
Output Skew; NOTE 3, 7
Multiple Frequency Skew;
NOTE 4, 7
Part-to-Part Skew; NOTE 5, 7
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
Output Frequency
Propagation Delay; NOTE 1
Bank Skew, NOTE 2, 7
Output Skew; NOTE 3, 7
Multiple Frequency Skew;
NOTE 4, 7
Part-to-Part Skew; NOTE 5, 7
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
DD
DD
= 3.3V ± 5%, V
= V
DDA
= V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
DDB
125MHz, 12kHz – 20MHz
125MHz, 12kHz – 20MHz
= V
DDA
DDC
Test Conditions
Test Conditions
= V
20% to 80%
20% to 80%
ƒ ≤ 250MHz
ƒ ≤ 250MHz
DDX
ƒ = 10MHz
ƒ = 10MHz
ƒ = 10MHz
ƒ = 10MHz
DDB
= 3.3V ± 5%, T
5
/2 of the output.
= V
DDC
DDX
= 2.5V ± 5%, T
/2.
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
A
= -40°C to 85°C
/2
/2
/2
/2
/2
/2
/2
/2
Minimum
Minimum
400
350
2.3
2.5
40
40
A
= -40°C to 85°C
ICS87946AYI-01 REV. BMAY 4, 2007
Typical
Typical
0.19
0.19
3.1
3.2
50
50
Maximum
Maximum
DDX
250
130
320
700
950
250
120
325
700
800
3.8
3.8
30
60
35
57
3
3
3
3
/2.
Units
Units
MHz
MHz
ns
ps
ps
ps
ps
ps
ps
ns
ns
ns
ps
ps
ps
ps
ps
ps
ns
ns
%
%

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