ICS87946AYI-01LF IDT, Integrated Device Technology Inc, ICS87946AYI-01LF Datasheet - Page 10

• Manufacturer Part Number: ICS87946AYI-01LF
• Description: IC CLOCK GENERATOR 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Clock Generatorr

Specifications of ICS87946AYI-01LF

• Pll: No
• Input: CML, LVPECL, SSTL
• Output: LVCMOS, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: Yes/No
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 250MHz
• Number Of Clock Inputs: 1
• Mode Of Operation: Differential
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 87946AYI-01LF

LVPECL Clock Input Interface
The PCLK /PCLK accepts LVPECL, CML, SSTL and other
differential signals. Both signals must meet the V
requirements. Figures 2A to 2F show interface examples for the
HiPerClockS PCLK/PCLK input driven by the most common driver
Figure 2A. HiPerClockS PCLK/PCLK Input
Figure 2C. HiPerClockS PCLK/PCLK Input
Figure 2E. HiPerClockS PCLK/PCLK Input
IDT™ / ICS™ 16:1, SINGLE-ENDED MULTIPLEXER
ICS87946I-01
LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
2.5V
3.3V
3.3V
LVPECL
SSTL
CML
Driven by an Open Collector CML Driver
Driven by a 3.3V LVPECL Driver
Driven by an SSTL Driver
Zo = 60Ω
Zo = 60Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
R3
120
2.5V
R3
125
3.3V
R1
120
R1
84
R1
50
3.3V
R4
120
R4
125
R2
120
R2
84
R2
50
PP
PCLK
nPCLK
PCLK
nPCLK
PCLK
nPCLK
and V
3.3V
3.3V
3.3V
HiPerClockS
Input
HiPerClockS
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
CMR
input
10
types. The input interfaces suggested here are examples only. If
the driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the driver
component to confirm the driver termination requirements.
Figure 2B. HiPerClockS PCLK/PCLK Input
Figure 2D. HiPerClockS PCLK/PCLK Input Driven by
Figure 2F. HiPerClockS PCLK/PCLK Input Driven by
3.3V
3.3V
3.3V LVPECL
3.3V
LVDS
CML Built-In Pullup
R5
100 - 200
Driven by a Built-In Pullup CML Driver
a 3.3V LVPECL Driver with AC Couple
a 3.3V LVDS Driver
Zo = 50Ω
Zo = 50Ω
R6
100 - 200
Zo = 50Ω
Zo = 50Ω
R5
100
Zo = 50Ω
Zo = 50Ω
ICS87946AYI-01 REV. BMAY 4, 2007
C1
C2
C1
C2
R3
84
3.3V
R1
125
R3
1k
3.3V
R1
100
R1
1k
R4
84
R2
125
R4
1k
R2
1k
PCLK
nPCLK
PCLK
nPCLK
3.3V
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
3.3V
3.3V
HiPerClockS
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK