MPC9608AC IDT, Integrated Device Technology Inc, MPC9608AC Datasheet - Page 3

• Manufacturer Part Number: MPC9608AC
• Description: IC CLOCK BUFFER ZD 1:10 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of MPC9608AC

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 1:10 LVCMOS Zero Delay Clock Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9608
1:10 LVCMOS Zero Delay Clock Buffer
MPC9608
476
Table 1. Pin Configuration
CCLK
FB_IN
F_RANGE[0:1]
BSEL
PLL_EN
OE
CLK_STOP
QA0-4, QB0-4
QFB
GND
V
V
Table 2. Function Table
Table 3. Clock Frequency Configuration for QFB Connected to FB_IN
F_RANGE[0]
CCA
CC
F_RANGE[0:1]
CLK_STOP
PLL_EN
Control
BSEL
Pin
OE
0
0
0
0
1
1
1
1
F_RANGE[1]
Input
Input
Input
Input
Input
Input
Input
Output
Output
Supply
Supply
Supply
Default
00
0
0
0
0
I/O
0
0
1
1
0
0
1
1
PLL frequency range. Refer to
f
Outputs enabled
Outputs enabled (active)
Normal operation mode with PLL enabled.
QB0-4
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
V
V
CC
CC
Type
= f
BSEL
QA0-4
0
1
0
1
0
1
0
1
PLL reference clock signal
PLL feedback signal input, connect to a QFB output
PLL frequency range select
Frequency divider select for bank B outputs
PLL enable/disable
Output enable/disable (high-impedance tristate)
Synchronous clock enable/stop
Clock outputs
PLL feedback signal output. Connect to FB_IN
Negative power supply
PLL positive power supply (analog power supply). The MPC9608 requires an external RC filter for
the analog power supply pin V
Positive power supply for I/O and core
0
100.0 – 200.0
range [MHz]
f
50.0 – 100.0
REF
25.0 – 50.0
12.5 – 25.0
(CCLK)
Table 3.Clock Frequency Configuration for QFB Connected to
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
3
Ratio
f
f
f
f
REF
REF
REF
REF
CCA.
f
Outputs synchronously stopped in logic low state
Outputs disabled (high-impedance state), independent on
CLK_STOP. Applying OE = 1 and PLL_EN = 1 resets the device.
The PLL feedback output QFB is not affected by OE.
Test mode with PLL disabled. CCLK is substituted for the internal
VCO output. MPC9608 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not applicable.
Applying OE = 1 and PLL_EN = 1 resets the device.
QB0-4
QA0-QA4
Refer to the Applications Information section for details.
= f
100.0 – 200.0
f
50.0 – 100.0
QA0-4
QA0-4
25.0 – 50.0
12.5 – 25
Function
÷ 2
[MHz]
f
f
f
f
REF
REF
REF
REF
Ratio
f
f
f
f
REF
REF
REF
REF
1
÷ 2
÷ 2
÷ 2
÷ 2
QB0-B4
100.0 – 200.0
f
50.0 – 100.0
50.0 – 25.0
25.0 – 50.0
25.0 – 50.0
12.5 – 25.0
12.5 – 25.0
6.25 – 12.5
QB0-4
FB_INT
[MHz]
NETCOM
QFB
f
f
f
f
f
f
f
f
REF
REF
REF
REF
REF
REF
REF
REF
MPC9608