ICS932S422CFLFT IDT, Integrated Device Technology Inc, ICS932S422CFLFT Datasheet - Page 18

• Manufacturer Part Number: ICS932S422CFLFT
• Description: IC PCIE GEN2 MAIN CLOCK 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of ICS932S422CFLFT

• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output: -
• Input: -
• Other names: 932S422CFLFT

PD De-assertion
1412A—12/10/07
The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300µs of PD deassertion.
Comments
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V (-0.3V) then use TEST_SEL
If power-up w/ V<2.0V (-0.3V) then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a real time input.
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B6b6.
If test mode is invoked by B6b6, only B6b7
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
Test Clarification Table
Integrated
Circuit
Systems, Inc.
CPU#, 133MHz
SRC# 100MHz
REF, 14.31818
CPU, 133MHz
SRC, 100MHz
USB, 48MHz
PCI, 33MHz
PWRDWN#
<1.8mS
Tstable
<300µS, >200mV
Tdrive_PwrDwn#
FSLC/TES
18
HW PIN
T_SEL
0
1
1
1
1
0
0
HW
FSLB/TES
T_MODE
HW PIN
X
X
X
0
0
1
1
ENTRY
TEST
B6b6
BIT
X
X
X
X
0
1
1
SW
REF/N or
B6b7
HI-Z
X
0
1
0
1
0
1
ICS932S422C
NORMAL
OUTPUT
REF/N
REF/N
REF/N
REF/N
HI-Z
HI-Z