ICS932S422CFLFT IDT, Integrated Device Technology Inc, ICS932S422CFLFT Datasheet - Page 17

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ICS932S422CFLFT

Manufacturer Part Number
ICS932S422CFLFT
Description
IC PCIE GEN2 MAIN CLOCK 56-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Generatorr
Datasheet

Specifications of ICS932S422CFLFT

Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Frequency-max
400MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output
-
Input
-
Other names
932S422CFLFT
PD Assertion
PD should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x
Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
See SMBus Byte 4 for additional information.
Notes:
1. Refer to SMBus Byte 4 for additional information.
1412A—12/10/07
PD, Power Down
PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down.
When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
CPU, SRC and PCI Divider Ratios
P
0
1
D
Div(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Integrated
Circuit
Systems, Inc.
I
e r
N
F
C
* f
r o
o l
P
m
t a
U
2
l a
r o
Divider
120
15
10
30
12
20
60
16
24
40
2
3
5
4
6
8
N
C
F
r o
P
o l
U
m
t a
CPU#, 133MHz
SRC#, 100MHz
REF, 14.31818
#
l a
CPU, 133MHz
SRC, 100MHz
USB, 48MHz
PCI, 33MHz
r o
N
I
e r
S
r o
PD
F
R
* f
m
o l
C
l a
t a
2
N
S
F
r o
R
o l
C
m
t a
#
l a
P
3
C
17
3
L
F I
M
o
w
P /
H
z
I C
4
U
8
L
REF Drive Strength Functionality
Byte6,
M
o
bit 4
S
w
B
H
0
1
1
1
1
z
Byte 10,
1
bit 1
4
X
0
0
1
1
3 .
R
L
1
o
E
8
w
F
M
H
Byte 10,
z
bit 0
X
N
0
1
0
1
ICS932S422C
o
e t
1
1
REF1
1x
1x
1x
2x
2x
REF0
1x
1x
2x
1x
2x

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