ICS87321AMI IDT, Integrated Device Technology Inc, ICS87321AMI Datasheet - Page 10

• Manufacturer Part Number: ICS87321AMI
• Description: IC CLK GEN /1 /2 DIFF 8-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Clock Generatorr

Specifications of ICS87321AMI

• Pll: No
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 700MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 800-1201; 800-1201-5; 800-1201; 87321AMI

R
I
LVCMOS C
All control pins have internal pulldowns; additional resistance is
not required but can be added for additional protection. A 1k
resistor can be used.
T
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
IDT
NPUTS
RTT =
ERMINATION FOR
ECOMMENDATIONS FOR
ICS87321I
÷1, ÷2 DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
™
/ ICS
((V
:
F
™
FOUT
IGURE
OH
3.3V LVPECL CLOCK GENERATOR
ONTROL
+ V
OL
3A. LVPECL O
) / (V
1
P
INS
3.3V LVPECL O
CC
Z
Z
– 2)) – 2
o
o
= 50
= 50
U
NUSED
Z
o
50
UTPUT
I
NPUT
T
RTT
ERMINATION
UTPUTS
50
P
V
INS
CC
FIN
- 2V
10
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion. Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
FOUT
F
IGURE
3B. LVPECL O
Z
Z
o
o
= 50
= 50
125
84
ICS87321AMI REV. A APRIL 7, 2009
UTPUT
3.3V
125
84
T
ERMINATION
FIN