ADF4112BRUZ Analog Devices Inc, ADF4112BRUZ Datasheet - Page 7

• Manufacturer Part Number: ADF4112BRUZ
• Description: IC SYNTH PLL RF 3.0GHZ 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4112BRUZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 3GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 3GHz
• Pll Type: Frequency Synthesis
• Frequency: 3GHz
• Supply Current: 6.5mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4112EBZ1 - BOARD EVAL FOR ADF4112EVAL-ADF411XEBZ1 - BOARD EVAL FOR ADF411X NO CHIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
TSSOP
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LFCSP
Pin No.
19
20
1
2, 3
4
5
6, 7
8
9, 10
11
12
13
14
15
16, 17
18
CPGND
AGND
RF
RF
REF
Figure 3. TSSOP Pin Configuration
AV
R
SET
IN
IN
CP
DD
IN
B
A
Mnemonic
R
CP
CPGND
AGND
RF
RF
REF
DGND
CE
CLK
LE
MUXOUT
DV
V
AV
DATA
1
2
3
4
5
6
7
8
SET
P
(Not to Scale)
IN
IN
DD
ADF4110
ADF4111
ADF4112
ADF4113
DD
TOP VIEW
B
A
IN
16
15
14
13
12
11
10
9
Function
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the R
So, with R
Charge Pump Output. When enabled, this provides ±I
drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 29.
Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin. AV
as DV
Reference Input. This is a CMOS input with a nominal threshold of V
resistance of 100 kΩ. See Figure 28. This input can be driven from a TTL or CMOS crystal oscillator,
or can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high powers up the device depending on the status of the power-
down Bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches; the latch is selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital
ground plane should be placed as close as possible to this pin. DV
as AV
Charge Pump Power Supply. This should be greater than or equal to V
3 V, V
I
V
DV
MUXOUT
LE
DATA
CLK
CE
DGND
CP
P
DD
max
DD
P
DD
can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.
=
.
.
R
SET
23
SET
5 .
= 4.7 kΩ, I
Rev. C | Page 7 of 28
CPmax
= 5 mA.
SET
ADF4110/ADF4111/ADF4112/ADF4113
pin is 0.56 V. The relationship between I
CPGND
AGND
AGND
RF
RF
IN
IN
B
A
Figure 4. LFCSP Pin Configuration
1
2
3
4
5
CP
to the external loop filter, which in turn
(Not to Scale)
ADF4110
ADF4111
ADF4112
ADF4113
TOP VIEW
DD
DD
DD
must be the same value
must be the same value
/2, and an equivalent input
DD
. In systems where V
15
14
13
12
11
MUXOUT
LE
DATA
CLK
CE
CP
and R
SET
is
DD
is