ADF4112BRUZ Analog Devices Inc, ADF4112BRUZ Datasheet - Page 13

• Manufacturer Part Number: ADF4112BRUZ
• Description: IC SYNTH PLL RF 3.0GHZ 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4112BRUZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 3GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 3GHz
• Pll Type: Frequency Synthesis
• Frequency: 3GHz
• Supply Current: 6.5mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4112EBZ1 - BOARD EVAL FOR ADF4112EVAL-ADF411XEBZ1 - BOARD EVAL FOR ADF411X NO CHIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 31 is a simplified
schematic. The PFD includes a programmable delay element
that controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
reference counter latch, ABP2 and ABP1, control the width of
the pulse. See Table 7.
CP OUTPUT
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4110 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Table 9 shows the full truth table. Figure 32 shows the
MUXOUT section in block diagram form.
R DIVIDER
N DIVIDER
R DIVIDER
N DIVIDER
HI
HI
Figure 31. PFD Simplified Schematic and Timing (In Lock)
D1
D2
CLR1
CLR2
U1
U2
Q1
Q2
PROGRAMMABLE
ABP1
UP
DOWN
DELAY
ABP2
U3
CPGND
V
P
CHARGE
PUMP
Rev. C | Page 13 of 28
CP
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive phase detector (PD) cycles is less
than 15 ns. With LDP set to 1, five consecutive cycles of less
than 15 ns are required to set the lock detect. It stays high until
a phase error greater than 25 ns is detected on any subsequent
PD cycle.
The N-channel open-drain analog lock detect should be
operated with a 10 kΩ nominal external pull-up resistor. When
lock has been detected, this output is high with narrow low-
going pulses.
ANALOG LOCK DETECT
INPUT SHIFT REGISTER
The ADF4110 family digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter comprised of
a 6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK MSB first. Data
is transferred from the shift register to one of four latches on
the rising edge of LE. The destination latch is determined by the
state of the two control bits (C2, C1) in the shift register. These
are the two LSBs, DB1 and DB0, as shown in Figure 2. The truth
table for these bits is shown in Table 5.
Table 6 shows a summary of how the latches are programmed.
Table 5. C2, C1 Truth Table
C2
0
0
1
1
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
Control Bits
ADF4110/ADF4111/ADF4112/ADF4113
C1
0
1
0
1
SDOUT
Data Latch
R Counter
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
Figure 32. MUXOUT Circuit
MUX
CONTROL
DV
DGND
DD
MUXOUT