ICS85454AK-01LF IDT, Integrated Device Technology Inc, ICS85454AK-01LF Datasheet - Page 5

• Manufacturer Part Number: ICS85454AK-01LF
• Description: IC MUX DUAL 2:1/1:2 16-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS85454AK-01LF

• Number Of Circuits: 2
• Ratio - Input:output: 2:1, 1:2
• Differential - Input:output: No/No
• Input: CML, LVDS, LVPECL
• Output: LVDS
• Frequency - Max: 2.5GHz
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-VFQFN
• Frequency-max: 2.5GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85454AK-01LF

The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the dBc Phase Noise. This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of
the noise power present in a 1Hz band at a specified offset
from the fundamental frequency to the power value of the
fundamental. This ratio is expressed in decibels (dBm) or a
As with most timing specifications, phase noise measure-
ments have issues. The primary issue relates to the limita-
tions of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
85454AK-01
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-190
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0
10
Integrated
Circuit
Systems, Inc.
100
1k
www.icst.com/products/hiperclocks.html
A
O
DDITIVE
FFSET
F
10k
ROM
P
C
HASE
5
ARRIER
ratio of the power in the 1Hz band to the power in the funda-
mental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the fre-
quency domain, we get a better understanding of its effects
on the desired application over the entire time record of the
signal. It is mathematically possible to calculate an expected
bit error rate given a phase noise plot.
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
J
F
ITTER
REQUENCY
100k
D
IFFERENTIAL
(H
Z
)
1M
622.08MHz (12kHz - 20MHz)
-
Additive Phase Jitter
TO
-LVDS M
ICS85454-01
= 0.05ps (typical)
10M
D
REV. B OCTOBER 28, 2008
UAL
ULTIPLEXER
2:1/1:2
at
100M