ICS8535AGI-01LF IDT, Integrated Device Technology Inc, ICS8535AGI-01LF Datasheet - Page 8
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ICS8535AGI-01LF
Manufacturer Part Number
ICS8535AGI-01LF
Description
IC FANOUT BUFFER 1-4 20-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Fanout Buffer (Distribution), Multiplexerr
Series
HiPerClockS™r
Datasheet
1.ICS8535AGI-01LFT.pdf
(16 pages)
Specifications of ICS8535AGI-01LF
Number Of Circuits
1
Ratio - Input:output
2:4
Differential - Input:output
No/Yes
Input
LVCMOS, LVTTL
Output
LVPECL
Frequency - Max
266MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Frequency-max
266MHz
Number Of Clock Inputs
2
Mode Of Operation
Single-Ended
Output Frequency
266MHz
Output Logic Level
LVPECL
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TSSOP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Signal Type
LVCMOS/LVTTL
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
8535AGI-01LF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS8535AGI-01LF
Manufacturer:
AKM
Quantity:
19
Company:
Part Number:
ICS8535AGI-01LFT
Manufacturer:
IDT
Quantity:
2 258
T
8535AGI-01
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
R
I
CLK I
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
ground.
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
RTT =
NPUTS
ERMINATION FOR
ECOMMENDATIONS FOR
NPUT
((V
:
F
FOUT
OH
IGURE
:
ONTROL
+ V
OL
2A. LVPECL O
) / (V
1
resistor can be used.
resistor can be tied from the CLK input to
P
INS
LVPECL O
CC
Z
Z
:
– 2)) – 2
o
o
= 50
= 50
U
NUSED
Z
o
50
UTPUT
UTPUTS
I
NPUT AND
T
A
RTT
ERMINATION
50
PPLICATION
V
CC
LVCMOS/LVTTL-
FIN
- 2V
O
UTPUT
www.idt.com
P
8
INS
I
drive 50 transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended that the
board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
NFORMATION
O
LVPECL O
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
UTPUTS
FOUT
F
IGURE
:
TO
UTPUT
-3.3V LVPECL F
2B. LVPECL O
:
Z
Z
o
o
= 50
= 50
125
84
UTPUT
ICS8535I-01
L
OW
3.3V
125
84
T
ANOUT
S
ERMINATION
KEW
REV. F OCTOBER 4, 2010
FIN
, 1-
B
UFFER
TO
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