ICS8535AG-21LF IDT, Integrated Device Technology Inc, ICS8535AG-21LF Datasheet

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ICS8535AG-21LF

Manufacturer Part Number
ICS8535AG-21LF
Description
IC CLOCK GEN 1-2 LVPECL 14-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet

Specifications of ICS8535AG-21LF

Number Of Circuits
1
Ratio - Input:output
2:2
Differential - Input:output
No/Yes
Input
LVCMOS, LVTTL
Output
LVPECL
Frequency - Max
266MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Frequency-max
266MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
8535AG-21LF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS8535AG-21LF
Manufacturer:
IDT
Quantity:
70
LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-
3.3V LVPECL CLOCK GENERATOR
General Description
single-ended clock input accepts LVCMOS or LVTTL input levels
and translate them to 3.3V LVPECL levels. The clock enable is
internally synchronized to eliminate runt clock pulses on the output
during asynchronous assertion/deassertion of the clock enable
pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8535-21 ideal for those applications demanding well defined
performance and repeatability.
Block Diagram
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
CLK_SEL
HiPerClockS™
CLK_EN
ICS
CLK0
CLK1
Pullup
Pulludown
Pulludown
Pulludown
The ICS8535-21 is a low skew, high performance
1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout
buffer and a member of the HiPerClockS™ family of
High Performance Clock Solutions from IDT. The
ICS8535-21 has two single-ended clock inputs. The
0
1
D
LE
Q
Q0
Q0
Q1
Q1
1
Features
4.40mm x 5.0mm x 0.925mm package body
Pin Assignment
Two differential 3.3V LVPECL outputs
Selectable CLK0 or CLK1 inputs for redundant and multiple
frequency fanout applications
CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 266MHz
Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels
Output skew: 20ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 1.6ns (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in both standard (RoHS 5) and lead-free (RoHS 6)
ICS8535-21 14 Lead TSSOP
CLK_SEL
CLK_EN
CLK0
CLK1
V
V
V
EE
CC
EE
G Package
Top View
1
2
3
4
5
6
7
ICS8535AG-21 REV. A FEBRUARY 24, 2009
14
13
12
11
10
9
8
V
Q0
Q0
nc
Q1
Q1
V
CC
CC
ICS8535-21

Related parts for ICS8535AG-21LF

ICS8535AG-21LF Summary of contents

Page 1

... Industrial temperature information available upon request • Available in both standard (RoHS 5) and lead-free (RoHS 6) Pin Assignment V EE CLK_EN CLK_SEL CLK0 CLK1 ICS8535-21 14 Lead TSSOP Q1 4.40mm x 5.0mm x 0.925mm package body 1 ICS8535- Package Top View ICS8535AG-21 REV. A FEBRUARY 24, 2009 ...

Page 2

... When LOW, selects CLK0 input. LVCMOS/LVTTL interface levels. Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. Power supply pins. Differential output pair. LVPECL interface levels. No connect. Differential output pair. LVPECL interface levels. Test Conditions 2 Minimum Typical Maximum ICS8535AG-21 REV. A FEBRUARY 24, 2009 Units pF Ω k Ω k ...

Page 3

... CLK0 or CLK1 Q0 LOW 1 HIGH IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER Selected Source Q0, Q1 CLK0 Disabled; Low CLK1 Disabled; Low CLK0 Enabled CLK1 Enabled Disabled Q0, Q1 HIGH LOW 3 Outputs Q0, Q1 Disabled; High Disabled; High Enabled Enabled Enabled ICS8535AG-21 REV. A FEBRUARY 24, 2009 ...

Page 4

... Test Conditions Minimum 3.135 = 3.3V ± 5 0°C to 70° Test Conditions Minimum 3.465 3.465 465V 465V Typical Maximum 3.3 3.465 50 Typical Maximum 0.3 CC -0.3 1.3 -0.3 0.8 150 5 -5 -150 ICS8535AG-21 REV. A FEBRUARY 24, 2009 Units V mA Units µA µA µA µA ...

Page 5

... Integration Range: 12kHz – 20MHz 20% to 80% @ 50MHz ƒ ≤ 200MHz 5 Minimum Typical Maximum V – 1.4 V – 0 – 2.0 V – 1 0.6 1.0 Minimum Typical Maximum 266 1.0 1.6 0.03 20 300 300 600 45 55 ICS8535AG-21 REV. A FEBRUARY 24, 2009 Units µA µA V Units MHz ...

Page 6

... It is mathematically possible to calculate an expected bit error rate given a phase noise plot. 10k 100k Offset Frequency (Hz) meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment 10M ICS8535AG-21 REV. A FEBRUARY 24, 2009 100M ...

Page 7

... R Output Rise/Fall Time IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER Par SCOPE Qx Qx Par nQx Part-to-Part Skew CLK0, CLK1 Q0, Q1 Q0, Q1 Propagation Delay Q0 Output Duty Cycle/Pulse Width/Period 7 tsk(pp PERIOD t PW odc = x 100% t PERIOD ICS8535AG-21 REV. A FEBRUARY 24, 2009 ...

Page 8

... FIN 50Ω RTT Figure 2B. 3.3V LVPECL Output Termination 8 3.3V 125Ω 125Ω 50Ω o FOUT Z = 50Ω o 84Ω 84Ω ICS8535AG-21 REV. A FEBRUARY 24, 2009 FIN ...

Page 9

... C2 C3 .1uF .1uF 10uf Figure 3. ICS8535-21 LVPECL Buffer Schematic Example IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER pin. For ICS8535-21, the unused clock outputs can be left floating. (U1-14) C4 .1uF Vcco = 3. 133 133 82.5 82.5 Optional Termination ICS8535AG-21 REV. A FEBRUARY 24, 2009 ...

Page 10

... IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER = 3. 3.465V, which gives worst case results 3.465V * 50mA = 173.25mW EE_MAX * Pd_total + θ vs. Air Flow JA 0 146.4°C/W 93.2°C/W 10 must be used. Assuming a moderate JA 200 500 125.2°C/W 112.1°C/W 85.5°C/W 81.2°C/W ICS8535AG-21 REV. A FEBRUARY 24, 2009 ...

Page 11

... IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER V OUT RL 50Ω – 0.9V CC_MAX = V – 1.7V CO_MAX ] * (V – [( CC_MAX OH_MAX CC_MAX – [(2V – (V CC_MAX OL_MAX CC_MAX L 11 – V ))/ – V OH_MAX CC_MAX OH_MAX L – V ))/ – V OL_MAX CC_MAX OL_MAX L ICS8535AG-21 REV. A FEBRUARY 24, 2009 ) = ) = ...

Page 12

... All Dimensions in Millimeters Symbol Minimum 0.5 A2 0.80 b 0.19 c 0. 0.45 α 0° aaa Reference Document: JEDEC Publication 95, MO-153 ICS8535AG-21 REV. A FEBRUARY 24, 2009 12 500 112.1°C/W 81.2°C/W Maximum 14 1.20 0.15 1.05 0.30 0.20 5.10 6.40 Basic 4.50 0.65 Basic 0.75 8° 0.10 ...

Page 13

... Shipping Packaging 14 Lead TSSOP 14 Lead TSSOP 2500 Tape & Reel “Lead-Free” 14 Lead TSSOP “Lead-Free” 14Lead TSSOP 2500 Tape & Reel 13 Temperature Tube 0°C to 70°C 0°C to 70°C Tube 0°C to 70°C 0°C to 70°C ICS8535AG-21 REV. A FEBRUARY 24, 2009 ...

Page 14

... Features Section - added lead-free bullet Added Recommendations for Unused Input and Output Pins Ordering Information Table - added lead-free part number, marking and note Ordering Information Table - added lead-free marking. IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER ICS8535AG-21 REV. A FEBRUARY 24, 2009 14 Date 12/5/05 6/4/07 ...

Page 15

ICS8535-21 LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United ...

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