ICS8535AGI-01LF IDT, Integrated Device Technology Inc, ICS8535AGI-01LF Datasheet
ICS8535AGI-01LF
Specifications of ICS8535AGI-01LF
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ICS8535AGI-01LF Summary of contents
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G D ENERAL ESCRIPTION The ICS8535I- low skew, high performance 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The ICS8535I-01 has two single ended clock inputs. the single ended clock input accepts LVCMOS or LVTTL input levels and translate them to ...
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ABLE IN ESCRIPTIONS ...
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T 3A ABLE ONTROL NPUT UNCTION ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS S y ...
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3.3V±5%, T ABLE HARACTERISTICS ...
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The spectral purity in a band at a specific offset from the fun- damental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most ...
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P ARAMETER LVPECL V EE -1.3V ± 0.165V 3. UTPUT OAD EST IRCUIT nQx Qx nQy Qy tsk( UTPUT KEW CLK0, CLK1 nQ0:nQ3 Q0: ROPAGATION ELAY ...
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R U ECOMMENDATIONS FOR NUSED I : NPUTS CLK I : NPUT For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection resistor can be tied ...
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S E CHEMATIC XAMPLE Figure 3 shows a schematic example of the ICS8535I-01. In this example, the CLK0 input is selected. The decoupling ca- 3. Ohm Ohm R13 43 R11 LVCMOS 1K F ...
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This section provides information on power dissipation and junction temperature for the ICS8535I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8535I-01 is the sum of the core power plus the power ...
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Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. F IGURE T o calculate worst case power dissipation into the ...
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ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains ...
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ACKAGE UTLINE UFFIX FOR T ABLE R EFERENCE 8535AGI-01 LVCMOS/LVTTL- -3.3V LVPECL F TO TSSOP EAD ACKAGE IMENSIONS ...
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ABLE RDERING NFORMATION ...
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" = ...
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We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...