ICS8737AG-11LFT IDT, Integrated Device Technology Inc, ICS8737AG-11LFT Datasheet - Page 8

• Manufacturer Part Number: ICS8737AG-11LFT
• Description: IC CLOCK GEN LVPECL 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of ICS8737AG-11LFT

• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Input: CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 650MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8737AG-11LFT

W
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
8737AG-11
RTT =
ERMINATION FOR
IRING THE
((V
F
FOUT
OH
IGURE
+ V
D
OL
3A. LVPECL O
IFFERENTIAL
) / (V
1
LVPECL O
CC
Z
Z
– 2)) – 2
CC
o
o
= 50
= 50
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
I
F
Z
NPUT TO
o
IGURE
50
UTPUT
UTPUTS
2. S
T
A
RTT
ERMINATION
A
CLK_IN
50
PPLICATION
INGLE
CCEPT
0.1uF
V
C1
CC
FIN
E
- 2V
D
NDED
S
IFFERENTIAL
INGLE
www.idt.com
S
IGNAL
R1
1K
V_REF
R2
1K
E
8
I
NDED
50 transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
NFORMATION
D
V
RIVING
CC
+
-
-
L
FOUT
TO
EVELS
F
- 3.3V LVPECL C
D
IGURE
IFFERENTIAL
3B. LVPECL O
Z
Z
o
o
= 50
= 50
I
NPUT
125
84
UTPUT
L
ICS8737-11
OW
3.3V
LOCK
125
84
T
S
ERMINATION
KEW
REV. C AUGUST 9, 2010
G
FIN
ENERATOR
, 1/ 2
CC
/2 is