ICS85314BGI-01LFT IDT, Integrated Device Technology Inc, ICS85314BGI-01LFT Datasheet - Page 9

• Manufacturer Part Number: ICS85314BGI-01LFT
• Description: IC FANOUT BUFFER 1-5 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS85314BGI-01LFT

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
• Output: LVPECL
• Frequency - Max: 700MHz
• Voltage - Supply: 2.375 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85314BGI-01LFT

W
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
85314BGI-01
R
I
CLK I
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
ground.
CLK/nCLK I
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
CLK to ground.
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
NPUTS
ECOMMENDATIONS FOR
IRING THE
NPUT
:
:
ONTROL
NPUT
D
IFFERENTIAL
:
resistor can be used.
resistor can be tied from the CLK input to
P
INS
:
U
NUSED
I
F
NPUT TO
IGURE
Single Ended Clock Input
resistor can be tied from
I
2. S
NPUT AND
A
A
PPLICATION
CCEPT
INGLE
D
IFFERENTIAL
E
O
C1
0.1u
S
NDED
UTPUT
INGLE
V_REF
CC
www.idt.com
/2 is
S
IGNAL
P
E
9
INS
I
NDED
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
O
LVPECL O
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
-
D
1K
R1
1K
R2
TO
UTPUTS
RIVING
VCC
L
-2.5V/3.3V LVPECL F
EVELS
D
CLK
nCLK
:
UTPUT
IFFERENTIAL
I
NPUT
CC
= 3.3V, V_REF should be 1.25V
ICS85314I-01
L
OW
ANOUT
S
KEW
REV. F JULY 25, 2010
, 1-
B
UFFER
TO
-5