ICS85314BGI-01LFT IDT, Integrated Device Technology Inc, ICS85314BGI-01LFT Datasheet - Page 11

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ICS85314BGI-01LFT

Manufacturer Part Number
ICS85314BGI-01LFT
Description
IC FANOUT BUFFER 1-5 20-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet

Specifications of ICS85314BGI-01LFT

Number Of Circuits
1
Ratio - Input:output
2:5
Differential - Input:output
Yes/Yes
Input
HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
Output
LVPECL
Frequency - Max
700MHz
Voltage - Supply
2.375 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Frequency-max
700MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
85314BGI-01LFT
T
85314BGI-01
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
RTT =
ERMINATION FOR
((V
FOUT
F
OH
IGURE
+ V
OL
4A. LVPECL O
) / (V
1
3.3V LVPECL O
CC
Z
Z
– 2)) – 2
o
o
= 50
= 50
Z
o
50
UTPUT
T
RTT
ERMINATION
UTPUTS
50
V
D
CC
FIN
- 2V
IFFERENTIAL
www.idt.com
11
50 transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
-
TO
-2.5V/3.3V LVPECL F
FOUT
F
IGURE
4B. LVPECL O
Z
Z
o
o
= 50
= 50
125
84
ICS85314I-01
UTPUT
L
OW
3.3V
T
125
84
ANOUT
ERMINATION
S
KEW
REV. F JULY 25, 2010
FIN
, 1-
B
UFFER
TO
-5

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